Patent US4085459A successfully refreshed from Google Patents.
US4085459A
Expired / Lapsed
US
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Multivalued data memory system using a charge coupled element
Assignee: Toshiba Corp
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Filing: 1976-09-10
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Granted: 1978-04-18
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Expires: 1996-09-10
Abstract
Abstract A memory system includes means for injecting a multivalued signal with at least three information carrying voltage levels, in the form of electric charge, to a charge coupled device (CCD); and a detection means for detecting a multivalued signal level read out from the output terminal of CCD and feeding the voltage of the level back to the injecting means. The detection means comprises a level detection section for generating a combination of outputs predetermined correspondingly to the multivalued signal level and an output section for generating upon receipt of the combination of outputs an output having a voltage level corresponding to the combination of outputs.
Inventors
- 👤 Kanji Hirabayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:49
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/454; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; G11C11/56; G11C11/565; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C19/34; G11C19/36; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
195 words
A memory system including a charge coupled device for storing in a channel of said charge coupled device an analog multivalued signal having at least three information carrying levels represented by an analog voltage level at the output terminal of said charge coupled device, said system comprising: injection means for injecting the multivalued signal in the form of electric charge into said charge coupled device; and detection means connected to the output terminal of said charge coupled device and adapted to detect the level of said multivalued signal and feed a voltage representing said level back to said injection means, said detection means including a level detection section having threshold detection means connected to the output terminal of said charge coupled device and constructed and arranged to simultaneously compare the voltage signal on said output terminal against at least two fixed voltage threshold levels and to generate a combination of binary outputs representing the multivalued signal level read out from the output terminal of said charge coupled device, and an output section for generating upon receipt of said combination of binary outputs an multivalued output having a voltage level corresponding to said combination of outputs.
Claim 2
Dependent Claim
195 words
A memory system including a charge coupled device for storing in a channel of said charge coupled device an analog multivalued signal having at least three information carrying levels represented by an analog voltage level at the output terminal of said charge coupled device, said system comprising: injection means for injecting the multivalued signal in the form of electric charge into said charge coupled device; and detection means connected to the output terminal of said charge coupled device and adapted to detect the level of said multivalued signal and feed a voltage representing said level back to said injection means, said detection means including a level detection section having threshold detection means connected to the output terminal of said charge coupled device and constructed and arranged to simultaneously compare the voltage signal on said output terminal against at least two fixed voltage threshold levels and to generate a combination of binary outputs representing the multivalued signal level read out from the output terminal of said charge coupled device, and an output section for generating upon receipt of said combination of binary outputs an multivalued output having a voltage level corresponding to said combination of outputs.
Claim 3
Dependent Claim
107 words
The memory system according to claim 1, in which said level detection section of said detection means includes a plurality of inverter circuits one less than the number of information levels of said multivalued signal, each of said inverter circuits including a field effect transistor whose gate electrode is coupled to the output terminal of said charge coupled device, the voltage threshold value of each of said field effect transistors being set to a different value which corresponds to the voltage level of said multivalued signal, the arrangement of said inverters permitting generation of said different combination of outputs corresponding to the voltage level to be detected.
Claim 4
Dependent Claim
171 words
The memory system according to claim 1, in which said level detection section of said detection means includes n number of flip-flop circuits one less than the number of information levels of said multivalued signal; each of said flip-flop circuit including means for supplying an amount of 1/n of charge supplied from the output terminal of said charge coupled device to one input terminal of the flip-flop circuit, means for supplying through a reference injector to the other input terminal of the flip-flop circuit an amount of charge to be compared with said amount of 1/n of charge which is supplied to said one input terminal of the flip-flop circuit, and means for taking out a comparison output corresponding to a difference between said amount of 1/n of charge supplied to said one input terminal of the flip-flop circuit and said amount of charge supplied to said other terminal of the flip-flop circuit, a combination of the comparison outputs from said flip-flop circuits corresponding to said predetermined different combination of outputs.
Claim 5
Dependent Claim
96 words
The memory system according to claim 1, in which said output section of said detection means includes output circuits equal in number to said information levels of said multivalued signals, each of said output circuits including a first field effect transistor to which a source voltage corresponding to one selected information level of said multivalued signal is supplied and at least one other field effect transistor connected in series to said first field effect transistor, said output circuits being controlled by said combination of outputs from said level detection section to generate said multivalued output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |