Patent US4085352A successfully refreshed from Google Patents.
US4085352A
Expired / Lapsed
US
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Digital waveform analyzer
Assignee: Individual
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Filing: 1976-10-12
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Granted: 1978-04-18
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Expires: 1996-10-12
Abstract
Abstract The Digital Waveform Analyzer is a solid state highly portable device that approximates the operation of a cathode ray oscilloscope in time sweep mode by selectively lighting elements of a rectangular matrix of light emitting diodes. The LED array has its rows driven by a vertical circuit and its columns driven by a horizontal circuit. The vertical circuit converts the analog input signal to a "one-of-N" digital code. The converter utilizes an array of comparators and exclusive OR gates and does not require clocking. The horizontal circuit which corresponds to the sweep section of a standard cathode ray oscilloscope has a variable frequency clock generator, a binary counter, a decoder and synchronizing circuits.
Inventors
- 👤 Richard Dickson Hilton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:13
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
184 words
A Digital Waveform Analyzer comprising: an input signal; a matrix of light emitting diodes wherein said LEDs are arranged in M columns and N rows; a vertical circuit which converts said input signal to a one-of-N digital code thereby driving said LED matrix rows and which compares said input signal against a select voltage to produce a synchronize signal; a horizontal circuit comprising: a column driving circuit outputting one-of-M code for driving said LED matrix columns; and, a sweep circuit comprised of: a variable frequency oscillator; a binary counter driven by said oscillator wherein the most significant bit of said counter is fed to said column driving circuit indicating if any LED column is to be illuminated, and wherein the remaining bits of said counter feed said column driving circuit indicating which, if any, LED column is to be illuminated; and, a synchronizing signal gate wherein said synchronize signal is gated with the most significant bit of said counter, said gate outputting a signal for clearing said counter and initiating a sweep; and power means for supplying power to said vertical and horizontal circuits.
Claim 2
Dependent Claim
184 words
A Digital Waveform Analyzer comprising: an input signal; a matrix of light emitting diodes wherein said LEDs are arranged in M columns and N rows; a vertical circuit which converts said input signal to a one-of-N digital code thereby driving said LED matrix rows and which compares said input signal against a select voltage to produce a synchronize signal; a horizontal circuit comprising: a column driving circuit outputting one-of-M code for driving said LED matrix columns; and, a sweep circuit comprised of: a variable frequency oscillator; a binary counter driven by said oscillator wherein the most significant bit of said counter is fed to said column driving circuit indicating if any LED column is to be illuminated, and wherein the remaining bits of said counter feed said column driving circuit indicating which, if any, LED column is to be illuminated; and, a synchronizing signal gate wherein said synchronize signal is gated with the most significant bit of said counter, said gate outputting a signal for clearing said counter and initiating a sweep; and power means for supplying power to said vertical and horizontal circuits.
Claim 3
Dependent Claim
50 words
The device of claim 1 wherein said sweep circuit includes a switching means which, when closed, inhibits oscillation in the absence of said synchronize signal and which, when open, allows said oscillator to be free running, said switch connected between said oscillator and the most significant bit of said counter.
Claim 4
Dependent Claim
89 words
The device of claim 1 wherein said vertical circuit comprises: means for providing a standard voltage array; a plurality of voltage comparators wherein said input signal is compared against said standard voltage array means and said comparators outputs indicate the instantaneous value of said input signal; means for converting said comparators outputs to a one-of-N digital code; a synchronizing level voltage means; and, a voltage comparator wherein said input signal is compared against the output of said synchronizing level voltage means and said comparator output is the synchronize signal.
Claim 5
Dependent Claim
50 words
The device of claim 3 wherein said sweep circuit includes a switching means which, when closed, inhibits oscillation in the absence of said synchronize signal and which, when open, allows said oscillator to be free running, said switch connected between said oscillator and the most significant bit of said counter.
Claim 6
Dependent Claim
17 words
The device of claim 3 including a gain control buffer means for accomodating said input signal amplitude.
Claim 7
Dependent Claim
50 words
The device of claim 5 wherein said sweep circuit includes a switching means which, when closed, inhibits oscillation in the absence of said synchronize signal and which, when open, allows said oscillator to be free running, said switch connected between said oscillator and the most significant bit of said counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |