Dynamic digital pulse display

Claim 2

An arrangement for the dynamic digital display of predetermined characteristics of a high frequency pulse train wherein a pulse sequence is applied to an equidistantly tapped delay line, comprising in combination a plurality of sets of bistable circuits, logic AND gates and amplifiers, the taps of said delay line being connected to the input of the associated amplifiers of all said sets, wherein the amplitude range of said pulse sequence is divisible into adjacent amplitude intervals whereby the amplifier of each of said sets generates an output signal only when an input of a predetermined level is provided from said delay line, a matrix of display indicators, said matrix of display indicators being arranged in a configuration of horizontal lines and vertical columns, and means responsive to a synchronizing pulse applied to the synchronizing line comprising one of said inputs to said bistable circuits for indicating the duration, spacing and amplitude characteristics of the signals in said pulse sequence said means including said indicator configuration in which said indicators are selectively energized in accordance with said characteristics of said pulse sequence at the time of said synchronization pulse.

Claim 3

An arrangement as described in claim 1 wherein the second input to said bistable circuit comprises the output of the associated logical and gate, and wherein the two inputs to said logical and gate comprise the synchronization signal line and the signal from said associated amplifier.

Claim 4

Arrangement for the dynamic direct digital display of pulse relations, characterized in that a signal line L is provided to which a pulse sequence 4-2 is applied, that the signal line L has a minimum length resulting from the product of the signal speed multiplied by the time basis of the pulse sequence, that the signal line is equidistantly tapped, that n sets (2/1, 2/2 ... 2/n) each with m bistable circuits (2/1-1-1 ... 2/1-1-m, 2/2-1-1 ... 2/2-1-m, ..., 2/n-1-1 to 2/n-1-m), m AND gates (2/1-2-1 to 2/1-2-m; ...; 2/n-2-1 to 2/n-2-m), and m amplifiers (2/1-3-1 to 2/1-3-m; ...; 2/m-3-; to 2/n-3-m) are provided, whereby the two inputs of each bistable circuit (2/p-1-k; p = 1, 2 to n; k = 1, 2 to m) are connected to the synchronization line S and to the output of the AND gate (2/p-2-k; p=1, 2 to n; k = 1, 2 to m) associated with it, and the two inputs of the AND gate (2/p-2-k; p = 1, 2 to n; k = 1, 2 to m) are connected to the synchronization line S and the output of an amplifier (2/p-3-k; p = 1, 2 to n; k = 1, 2 to m) associated with the latter AND gate, that the kth (k = 1, 2 to m) of all taps L1, L2 to Lm of the signal line L is linked with the input of the kth (k = 1, 2 to m) amplifier of all sets (2/1, 2/2 to 2/n), that the amplitude range of the signal sequence 4-2 is divisible into n adjacent amplitude interval I1, I2 to In, that by means of the amplifier of the pth set (p = 1, 2 to n) an output signal is generatable for the pth amplitude interval only (p = 1, 2 to n), that in the output of each bistable circuit (2/p-1-k; p = 1, 2 to n; k = 1, 2 to m) an optical display element (1 2/p-k; p = 1, 2 to n; k = 1, 2 to m) is arranged, and that all optical display elements (1 2/1-1 to 1 2/n - m) are arranged in a field 1 of n lines and m columns, so that the time and amplitude relations of the wave form of the signal sequence (4/2) are permanently visually displayed by means of the optical display elements set according to the wave form of the signal sequence (4/2) at the time of the synchronization pulse.

Claim 5

Arrangement for the dynamic direct digital display of pulse relations, characterized in that a signal line L is provided to which a pulse sequence 4-2 is applied, that the signal line L has a minimum length resulting from the product of the signal speed multiplied by the time basis of the pulse sequence, that the signal line is equidistantly tapped, that n sets (2/1, 2/2 ... 2/n) each with m bistable circuits (2/1-1-1 ... 2/1-1-m, 2/2-1-1 ... 2/2-1-m, ..., 2/n-1-1 to 2/n-1-m), m AND gates (2/1-2-1 to 2/1-2-m; ...; 2/n-2-1 to 2/n-2-m), and m amplifiers (2/1-3-1 to 2/1-3-m; ...; 2/m-3-; to 2/n-3-m) are provided, whereby the two inputs of each bistable circuit (2/p-1-k; p = 1, 2 to n; k = 1, 2 to m) are connected to the synchronization line S and to the output of the AND gate (2/p-2-k; p=1, 2 to n; k = 1, 2 to m) associated with it, and the two inputs of the AND gate (2/p-2-k; p = 1, 2 to n; k = 1, 2 to m) are connected to the synchronization line S and the output of an amplifier (2/p-3-k; p = 1, 2 to n; k = 1, 2 to m) associated with the latter AND gate, that the kth (k = 1, 2 to m) of all taps L1, L2 to Lm of the signal line L is linked with the input of the kth (k = 1, 2 to m) amplifier of all sets (2/1, 2/2 to 2/n), that the amplitude range of the signal sequence 4-2 is divisible into n adjacent amplitude interval I1, I2 to In, that by means of the amplifier of the pth set (p = 1, 2 to n) an output signal is generatable for the pth amplitude interval only (p = 1, 2 to n), that in the output of each bistable circuit (2/p-1-k; p = 1, 2 to n; k = 1, 2 to m) an optical display element (1 2/p-k; p = 1, 2 to n; k = 1, 2 to m) is arranged, and that all optical display elements (1 2/1-1 to 1 2/n - m) are arranged in a field 1 of n lines and m columns, so that the time and amplitude relations of the wave form of the signal sequence (4/2) are permanently visually displayed by means of the optical display elements set according to the wave form of the signal sequence (4/2) at the time of the synchronization pulse.

Claim 6

Arrangement in accordance with claim 3, characterized in that only one set (n=1) of bistable circuits (1/1 to 1/m to which an associated AND gate (3/1 to 3/m) is connected, is required for determination of the pulse width and the pulse spacing characteristics of digital pulses which are displayed by selective energization of said optical display elements.

Claim 7

Arrangement in accordance with claim 3, characterized in that for generating the synchronization pulse, a delay circuit (6) to be activated before the beginning of the pulse sequence is provided, and that the synchronization pulse is generatable after the pulse sequence has been partly or fully fed into the pulse line (L).

Claim 8

Arrangement in accordance with claim 3, characterized in that the delay time of the delay circuit (6) is variable, so that at the ratio delay time shorter than the time basis of the pulse sequence, for successive pulse sequences the pulse relations of the last part of a preceding pulse sequence and the first part of the subsequent pulse sequence can be observed.

Claim 9

Arrangement in accordance with claim 3, characterized in that for generating a short synchronization pulse, and AND gate (5) is provided which is activated by a trigger pulse on a first input line (7), and that to block the AND gate, a circuit (8) generates a blocking signal on a further input line (9) after a short time starting with the emission of the trigger pulse.

Claim 10

Arrangement in accordance with claim 3, characterized in that for the recurring or non-recurring generation of a synchronization signal, the AND gate (5) with its input line (7) carrying the trigger pulse is controllable via the output (12) of a bistable circuit (11), whereby the bistable circuit (11) is controllable by means of the trigger signal on the one hand and externally, for predeterminined periods of time, for the generation of a blocking signal on the other.