Charge transfer device

Claim 2

A charge transfer device comprising: a semiconductor substrate; at least two arrays of charge transfer devices disposed on said semiconductor substrate; a clock pulse generator circuit disposed on said semiconductor substrate and driving simultaneously said at least two arrays of charge transfer devices, said clock pulse generator circuit being divided into at least two blocks arranged on said substrate so as to confine said at least two arrays of charge transfer devices therebetween; and a conductor line for supplying master clock pulses for externally controlling said at least two blocks of said clock pulse generator.

Claim 3

A charge transfer device according to claim 1, further comprising a conductor line for setting the initial value, said conductor line connecting said at least two blocks and being disposed on said substrate so as not to intersect with said conductor line for master clock pulses.

Claim 4

A charge transfer device according to claim 2, further comprising at least two input lines on said substrate each input line intersecting said conductor line for master clock pulses and said conductor line for setting an initial value.

Claim 5

A charge transfer device according to claim 2, further comprising at least two bonding pads for input pulses disposed in an area of said substrate bounded by said conductor line for setting an initial value and conductor lines connecting each of said at least two blocks with one of said at least two arrays of charge transfer devices, said bonding pads being connected electrically with one of said at least two arrays of charge transfer devices so as not to intersect any of said conductor lines.

Claim 6

A charge transfer device according to claim 1, in which each block of said clock pulse generator circuit consists of a pulse-forming circuit, a shift register connected to said pulse-forming circuit, delay circuits connected to respective stages of said shift registers and push-pull buffers connected to said respective stages of said shift register and said delay circuits for generating four-phase clock pulses, said shift register consisting of a plurality of inverter circuits connected one after another so as to divide the master clock pulse frequency by two and to generate pulses with a 50% duty ratio, said delay circuits introducing a slight delay in four phases, utilizing the delay time of the inverter circuits.

Claim 7

A charge transfer device according to claim 1, further comprising an input line connected in common to one end of each of said arrays, and an output line connected in common to the other end of each of said arrays, said arrays being displaced relative to one another so that the clock pulse applied to the first stage of one array is applied to the last stage of the adjacent array and clock pulses applied to the first stage of each respective array are shifted in time relative to each other by 180°

Claim 8

A charge transfer device according to claim 1, wherein each block of said clock pulse generator circuit comprises a plurality of inverter circuit stages, made of an enhancement/depletion-connected field effect transistor, connected in cascade, each block receiving said master clock pulses and generating plural clock pulses shifted in time with respect to each other from said inverter circuit stages.