US3857045A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four-phase logic systems
Assignee: National Aeronautics and Space Administration
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Filing: 1973-04-17
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Granted: 1974-12-24
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Expires: 1993-04-17
Abstract
Abstract A four-phase logic system is provided which includes at least four logic networks connected in parallel between a single power line and a reference potential. A four-phase clock generator generates four distinct clock signals from a single-phase clock input at data rate. Each logic network comprises a pair of complementary metal-oxide-semiconductor integrated transistors (CMOST). Each metal-oxide-semiconductor transistor (MOST) in the pair is responsive to a clock signal which turns the transistor ON or OFF. In each network there is also at least one MOST which is responsive to a logic signal. The logic transistor is connected in cascade with the pair of CMOSTs. A stray capacitance which serves as a storage capacitor between the junction of the pair of transistors and a reference potential provides an output signal dependent upon the applied clock signals and the incoming logic signal.
Inventors
- 👤 G Low
- 👤 H Petersen
- 👤 D Kinell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
A four-phase logic system comprising: at least four logic networks connected in parallel between a voltage source and a reference potential; each said logic network including a pair of CMOSTS, and a logic MOST circuit connected in series with the pair of CMOSTS, and wherein each said pair comprises a P type conductivity transistor and an N type conductivity transistor with their conductive paths in series connection adjacent series CMOST pairs and logic MOSTS alternating in position in said series between said voltage source and said reference potential, a four-phase clock generator adapted to generate a four-phase clock waveform signal from a single phase input clock waveform signal, each said CMOST in each pair of CMOSTS being respectively coupled to adjacent phases of said clock generator which turns it ON and OFF. each said logic MOST circuit being responsive to a logic input signal, and each junction terminal between each pair of CMOSTS constituting an output terminal for its associated logic network with the stray capacitance between said junction terminal and the reference potential constituting a storage means for storing the desired logic output of said associated logic network where it is available for readout from said output terminal.
Claim 2
Dependent Claim
199 words
A four-phase logic system comprising: at least four logic networks connected in parallel between a voltage source and a reference potential; each said logic network including a pair of CMOSTS, and a logic MOST circuit connected in series with the pair of CMOSTS, and wherein each said pair comprises a P type conductivity transistor and an N type conductivity transistor with their conductive paths in series connection adjacent series CMOST pairs and logic MOSTS alternating in position in said series between said voltage source and said reference potential, a four-phase clock generator adapted to generate a four-phase clock waveform signal from a single phase input clock waveform signal, each said CMOST in each pair of CMOSTS being respectively coupled to adjacent phases of said clock generator which turns it ON and OFF. each said logic MOST circuit being responsive to a logic input signal, and each junction terminal between each pair of CMOSTS constituting an output terminal for its associated logic network with the stray capacitance between said junction terminal and the reference potential constituting a storage means for storing the desired logic output of said associated logic network where it is available for readout from said output terminal.
Claim 3
Dependent Claim
124 words
A four-phase logic system as defined in claim 1 wherein first and second phases of said clock generator output are coupled to different control electrodes of the pair of said CMOSTS in the first of said logic networks, second and third phases of said clock generator output are coupled to different control electrodes of the pair of said CMOSTS in the second of said logic networks, third and fourth phases of said clock generator output are coupled to different control electrodes of the pair of said CMOSTS in the third of said logic networks, and said first and fourth phases of said clock generator output are coupled to different control electrodes of the pair of said CMOSTS in the fourth of said logic networks.
Claim 4
Dependent Claim
87 words
A four-phase logic system as defined in claim 2 wherein an electrode of the serially connected pair of CMOSTS of said first logic network and said third logic network are coupled directly to said voltage source in a conductive path therewith and said voltage source is coupled directly to an electrode in the conductive path of a logic MOST in the logic MOST circuit of said second logic network and to an electrode in the conductive path of the logic MOST circuit of said fourth logic network.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-23 | 1978-06-24 | 1978-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-23 | 1982-06-24 | 1982-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-23 | 1986-06-24 | 1986-12-24 | $7700.00 | Window Closed / Lapsed |