Patent US4081817A successfully refreshed from Google Patents.
US4081817A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Toshiba Corp
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Filing: 1976-08-24
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Granted: 1978-03-28
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Expires: 1996-08-24
Abstract
Abstract An insulated gate FET comprises a semiconductor substrate, source and drain regions formed in the surface of the semiconductor substrate in a manner spaced at a prescribed interval from each other, and a gate electrode provided on a surface portion of the substrate between the source and drain regions through an insulation layer. Depletion layers formed by the action of a buit-in-field are spread, respectively, into said semiconductor substrate from the source and drain regions, and these two depletion layers contact each other.
Inventors
- 👤 Hisashi Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
164 words
An insulated gate field effect transistor capable of miniaturization in which variations in the gate threshold voltage are maintained very small in spite of changes in channel length, comprising: a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed in a first surface of said substrate, and spaced a predetermined distance apart, a channel region formed in said substrate between said source and drain regions, said channel region less than 4 microns in length: an insulated gate electrode coupled to said first surface of said semi-conductor substrate adjacent said channel region, said source and drain regions having impurity concentrations much higher than that of said substrate so that depletion layers are formed in said substrate, said depletion layers spreading into said substrate from said source and drain regions, and joining one another in said channel region, whereby variations in said gate threshold voltage are maintained small in spite of changes in length of said channel region.
Claim 2
Dependent Claim
164 words
An insulated gate field effect transistor capable of miniaturization in which variations in the gate threshold voltage are maintained very small in spite of changes in channel length, comprising: a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type formed in a first surface of said substrate, and spaced a predetermined distance apart, a channel region formed in said substrate between said source and drain regions, said channel region less than 4 microns in length: an insulated gate electrode coupled to said first surface of said semi-conductor substrate adjacent said channel region, said source and drain regions having impurity concentrations much higher than that of said substrate so that depletion layers are formed in said substrate, said depletion layers spreading into said substrate from said source and drain regions, and joining one another in said channel region, whereby variations in said gate threshold voltage are maintained small in spite of changes in length of said channel region.
Claim 3
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein said semiconductor substrate is a p type impurity semiconductor substrate, and said source and drain regions are each an n type semiconductor region.
Claim 4
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein said semiconductor substrate in an n type impurity semiconductor substrate, and said source and drain regions are each a p type semiconductor region.
Claim 5
Dependent Claim
47 words
A semiconductor device according to claim 1 wherein in said channel region produced between said source and drain regions, the impurity concentration of said semiconductor substrate is 10 16 (cm -3 ) or less, and the length of said channel region is between 0.3 and 4 microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-27 | 1981-09-26 | 1982-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-27 | 1985-09-26 | 1986-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-27 | 1989-09-26 | 1990-03-28 | $7700.00 | Window Closed / Lapsed |