Inverter circuit control circuit for precluding simultaneous conduction of thyristors

Claim 2

In a circuit for supplying an alternating current to a load which includes two power supply terminals and first and second gate-controlled thyristor switches, each said switch having a gate electrode, a main conduction path and an associated turn-off time, the main conduction paths of said switches being connected in series between said terminals with each path having a commutating diode in inverse-parallel connection therewith, an improved control network for applying complementary signals to the gate electrodes of said switches to preclude their simultaneous conduction, said control network comprising: means in series with said load for sensing the current through said load; means responsive to said current sensing means for producing a trigger pulse at each zero crossing of said current; means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn off time of said switches; first means responsive to the cessation of each alternate one of said delay signals for producing a first signal at the gate electrode of said first switch to render it conductive; and second means responsive to the cessation of each of the remaining alternate delay signals for producing a second signal at the gate electrode of said second switch to render it conductive.

Claim 3

The combination of claim 1 wherein said current sensing means comprises a transformer having a primary winding serially connected with said load, and a centertapped secondary winding having first and second output terminals, the center-tap of said secondary winding being connected to a reference potential with the signal appearing at said first output terminal being phase shifted by 180 electrical degrees relative to the signal appearing at said second output terminal.

Claim 4

The combination of claim 1 wherein said trigger pulse producing means comprises, in combination: means responsive to the current through said load for producing a first wave, said first wave having the same frequency as said current and varying in amplitude between two voltage levels; means responsive to the current through said load for producing a second wave whose instantaneous value is the complement of said first wave; a first differentiator circuit coupled to said first wave, said first differentiator producing a first voltage pulse for each transition of said wave voltage from its first to its second level; a second differentiator circuit coupled to said second wave, said second differentiator producing a second voltage pulse for each transition of said wave voltage from its first to its second level; and means responsive to said first and second voltage pulses for producing said trigger pulse.

Claim 5

The combination of claim 3 where said means for producing a first wave comprises a first high gain limiting amplifier, said amplifier being connected to the first output terminal of said transformer secondary winding.

Claim 6

The combination of claim 3 where said means for producing a second wave comprises a second high gain limiting amplifier, said amplifier being connected to the second output terminal of said transformer secondary winding.

Claim 7

The combination of claim 1 where said means for producing a pulse comprises a monostable multivibrator coupled to said means for producing a trigger pulse, said multivibrator output pulse width having a width at least as great as the turn off time of said switches.

Claim 8

The combination of claim 1 where said first means for producing a signal at the gate electrode of said first switch comprises in combination: a bistable multivibrator, said multivibrator having first and second output terminals, said first terminal signal being the logical complement of said second terminal signal; and first amplifier means coupled between said bistable multivibrator first terminal and said first switch gate electrode.

Claim 9

The combination of claim 7 where said second means for producing a signal at the gate electrode of said second switch comprises, in combination: second amplifier means coupled between said bistable multivibrator second output and said second switch gate electrode.

Claim 10

A resonant inverter circuit for converting a dc or rectified low frequency ac voltage to a relatively high frequency voltage comprising, in combination: first and second power supply terminals; first and second control voltage responsive switches, each switch having a control electrode and a main conduction path that passes current more readily in one direction than in the other and an associated turn off time, said switches having their main conduction paths serially connected between said first and second terminals; first and second capacitors serially connected between said first and second terminals; an induction coil connected between the common connection of said first and second switches and the common connection of said first and second capacitors forming a resonant circuit thereby; first and second nonlinear devices, said devices passing current more readily in one direction than in the other, said first and second devices being connected in inverse-parallel with the main conductive paths of said first and second switches, respectively; means for continuously sensing the flow of current through said coil to produce a trigger pulse each time said current reduces to zero; means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn-off time of said switches; and means responsive to the cessation of each said delay signal for producing alternate signals at the gate electrodes of said first and second switches, respectively, to render each said switch separately conductive after an interval equal to the duration of said delay signal from the time current through said coil reduces to zero.

Claim 11

A resonant inverter circuit for converting a dc or rectified low frequency ac voltage to a relatively high frequency voltage comprising, in combination: first and second power supply terminals; first and second control voltage responsive switches, each switch having a control electrode and a main conduction path that passes current more readily in one direction than in the other and an associated turn off time, said switches having their main conduction paths serially connected between said first and second terminals; first and second capacitors serially connected between said first and second terminals; an induction coil connected between the common connection of said first and second switches and the common connection of said first and second capacitors forming a resonant circuit thereby; first and second nonlinear devices, said devices passing current more readily in one direction than in the other, said first and second devices being connected in inverse-parallel with the main conductive paths of said first and second switches, respectively; means for continuously sensing the flow of current through said coil to produce a trigger pulse each time said current reduces to zero; means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn-off time of said switches; and means responsive to the cessation of each said delay signal for producing alternate signals at the gate electrodes of said first and second switches, respectively, to render each said switch separately conductive after an interval equal to the duration of said delay signal from the time current through said coil reduces to zero.

Claim 12

The combination recited in claim 9 where said first and second control voltage responsive switches comprise silicon controlled rectifiers.

Claim 13

The combination recited in claim 9 where said first and second nonlinear devices comprise diodes.

Claim 14

The combination of claim 9 wherein said current sensing means comprises, in combination: a transformer having a primary winding and a secondary winding, said primary winding being connected in series with said induction coil so said coil current flows through said primary winding, said secondary winding having first and second terminals at respective ends thereof and having a third terminal at a center-tap thereof, said third terminal being connected to a reference potential; first threshold means connected to said secondary winding first terminal for producing a voltage at a first level whenever current through said first terminal is greater than a reference level and at a second level whenever current through said first terminal is less than said reference level; second threshold means connected to said secondary winding second terminal for producing a voltage at said first level whenever current through said second terminal is greater than said reference level and at said second level whenever current through said second terminal is less than said reference level; and means responsive to the transition of voltage produced by said first and second threshold means from said first level to said second level for producing said trigger pulse.

Claim 15

The combination of claim 12 where said first and second threshold means each comprises a high gain limiting amplifier.

Claim 16

The combination of claim 12 where said trigger pulse producing means comprises in combination: a first differentiator circuit having an input coupled to said first threshold means and having an output; a second differentiator circuit having an input coupled to said second threshold means and having an output; a logic OR gate having first and second input terminals connected to the outputs of said first differentiator and said second differentiator respectively, said logic gate having an output terminal at which an output signal is supplied whenever a signal of sufficient amplitude is present at said first or second terminal.

Claim 17

The combination of claim 14 where said delay signal producing means comprises in combination: a monostable multivibrator to which the output terminal of said OR gate is coupled, for producing a pulse in response to said OR gate output signal, said pulse having a width at least as great as the turn off time of said first and second switches.

Claim 18

The combination of claim 15 where said alternating signals producing means comprises in combination: a first bistable multivibrator having first and second output terminals, the signal at said first terminal being the logical complement of the signal at said second terminal; first amplifier means with an input to which the first output terminal of said first bistable multivibrator is coupled and with an output coupled to the control electrode of said first control voltage responsive switch; and second amplifier means to which the second output terminal of said bistable multivibrator is coupled and with an output coupled to the control electrode of said second control voltage responsive switch.

Claim 19

The combination of claim 16 further including means for interrupting operation of the inverter if said load current exceeds a predetermined level comprising, in combination: a rectifier circuit, said rectifier coupled to the secondary winding of said transformer, and producing an output voltge proportional to the amplitude of said load current; a threshold detector circuit, said detector coupled to said rectifier and producing an output voltage whenever said rectifier output exceeds a predetermined level; a second bistable multivibrator having first and second input terminals and a single output terminal, said multivibrator first input terminal coupled to said detector and producing an output voltage corresponding to a first logic level whenever said detector output voltage is present and a voltage corresponding to a second logic level otherwise; an INHIBIT logic circuit, said circuit having a first and second intput terminals, said INHIBIT first input terminal connected to the output of said monostable multivibrator, said INHIBIT second input terminal connected to said second bistable multivibrator output and said INHIBIT circuit output connected to the input of said first bistable multivibrator, said INHIBIT circuit preventing said monostable multivibrator pulses from triggering said first bistable multivibrator when said second bistable output voltage corresponds to a first logic level and allows said pulses to trigger said first bistable multivibrator otherwise.

Claim 20

The combination of claim 17 further including a circuit for varying the output power of said inverter comprising, in combination: an oscillator having output pulses whose voltage varies between a first and a second voltage level; a differentiator circuit coupled to said oscillator for producing a voltage that represents the time derivative of said oscillator voltage; amplifier means coupled to said differentiator circuit, said amplifier output coupled to the second input terminal of said second bistable multivibrator thereby setting said multivibrator to a voltage corresponding to a second logic level; a voltage ramp generator coupled to said amplifier output, said voltage ramp initiated by said amplifier output, where the slope of said ramp is variable; and threshold means responsive to said ramp generator for producing an output voltage whenever said ramp voltage exceeds a predetermined level, said voltage coupled to the first input of said second bistable multivibrator thereby setting said multivibrator to a voltage corresponding to a first logic level whenever said threshold means output voltage is present.

Claim 21

The power circuit of claim 18 further including one or more capacitors coupled across each of said first and second capacitors by switching means whereby said power is increased when said switching means are closed and decreased when said switching means are open.

Claim 22

In a circuit of the type wherein AC voltage is impressed across a load from a DC source through a switching network which includes series-connected thyristors, each having a commutating diode in inverse-parallel conduction with its principal conduction path, and a resonant circuit having capacitance and inductance disposed therein, an improved control network for applying complementary signals to the gates of the thyristors to preclude their simultaneous conduction, said control network including: means for generating a square wave upon the occurance of each zero current crossing through the load, the duration of said square wave being at least equal to the maximum turn off time of the thyristors; and means for alternating complementary output signals in response to the trailing edge of sequential signals from said square wave generating means, said complementary output signals being separately applied to the thyristor gates.

Claim 23

In a circuit of the type wherein AC voltage is impressed across a load from a DC source through a switching network which includes series-connected thyristors, each having a commutating diode in inverse-parallel conduction with its principal conduction path, and a resonant circuit having capacitance and inductance disposed therein, an improved control network for applying complementary signals to the gates of the thyristors to preclude their simultaneous conduction, said control network including: means for generating a square wave upon the occurance of each zero current crossing through the load, the duration of said square wave being at least equal to the maximum turn off time of the thyristors; and means for alternating complementary output signals in response to the trailing edge of sequential signals from said square wave generating means, said complementary output signals being separately applied to the thyristor gates.

Claim 24

The circuit of claim 20 wherein inductance for the resonant circuit includes a primary winding on a transformer serially connected to the load and wherein a secondary winding on said transformer is center-tapped to a reference potential in said square wave generating means with signals of complementary phase separately appearing from the end terminals thereof.

Claim 25

The circuit of claim 21 wherein the square wave generating means further includes a monostable multivibrator having the output therefrom connected to the input of said means for alternating complementary output signals and having the input thereto connected to output from an OR gate, said end terminals on said secondary winding each being connected separately to the inputs of said OR gate through respective zero crossing detection means.

Claim 26

The circuit of claim 22 wherein said monostable multivibrator includes means for varying the duration of output pulses therefrom to thereby determine the periods of conduction through both the commutating diodes and the thyristors.

Claim 27

The circuit of claim 23 wherein means for periodically inhibiting transfer of signals from said square wave generating means to said complementary output signals means establishes a power regulating duty cycle.

Claim 28

The circuit of claim 20 wherein means for periodically inhibiting transfer of signals from said square wave generating means to said complementary output signals means establishes a power regulating duty cycle.