Inverter adaptive lock-out technique

Claim 2

In a commutation control apparatus for an inverter circuit comprising first and second load current carrying gate controlled rectifier means connected serially across a source of direct current electric power and first and second commutating gate controlled rectifier means serially connected across said source and commutating circuit means interconnecting the respective junctions of said load current carrying and of said commutating gate controlled rectifier means, said commutation control apparatus being responsive to applied inverter command signals for firing said gate controlled rectifier means in predetermined sequence and comprising: a. lock-out control means to inhibit firing of said second commutating rectifier means for a period of time commencing upon firing of said first commutating rectifier means and terminating upon the occurrence of a turnoff signal; b. commutating detection means for providing a commutation signal upon detection of a condition in said inverter circuit indicative of the application of a reverse voltage across said first commutating rectifier means to initiate its turnoff; and c. gating means coupled to said commutating detection means and responsive solely to a commutation signal occurring after a predetermined first time interval subsequent to firing said first commutAting gate controlled rectifier means to produce said turnoff signal.

Claim 3

The arrangement of claim 1 wherein said first time interval is longer than the minimal time duration of commutating current flow subsequent to firing said first commutating gate controlled rectifier means.

Claim 4

The apparatus of claim 1 wherein said lock-out control means is arranged to terminate said inhibit period upon the expiration of a predetermined second time interval subsequent to firing said first commutating rectifier means in the absence of an earlier turnoff signal, said second time interval being longer than said first time interval.

Claim 5

The arrangement of claim 1, wherein said gating means comprises time delay means for delaying said turnoff signal for a predetermined turnoff interval subsequent to occurrence of said commutation signal.

Claim 6

The arrangement of claim 4 wherein said time delay means comprises unilateral conduction means connected to rapidly reset said time delay means upon removal of the reverse voltage across said first commutating rectifier means.

Claim 7

In a commutation control apparatus for an inverter circuit comprising first and second load current carrying gate controlled rectifier means connected serially across a source of direct current electric power and first and second commutating gate controlled rectifier means serially connected across said source and commutating circuit means interconnecting the respective junctions of said load current carrying and of said commutating gate controlled rectifier means, said commutation control apparatus being responsive to applied inverter command signals for firing saaid gate controlled rectifier means in predetermined sequence and comprising: a. commutating detection means for providing a commutation signal upon detection of a condition in said inverter circuit indicative of the application of a reverse voltage across said first commutating rectifier means to initiate its turnoff; b. gating means responsive to said commutation signal and adapted to provide at its output a turnoff signal occurring at a turnoff time interval subsequent to the occurrence of said commutation signal; c. lock-out signal means for generating a lock-out signal and responsive to said turnoff signal to switch the level of said lock-out signal from a first to a second state; d. lock-out circuit means for inhibiting firing of said second commutating recrifier means upon firing of said first commutating rectifier until such time as the state of said lock-out signal is switched from said first to said second state; e. pulse generating means for generating a predetermined output signal having a change of state upon expiration of a predetermined first time interval subsequent to firing of said first commutating rectifier means, and f. said gating means being responsive to said output signal and to said lock-out signal for applying said turnoff signal to said lock-out signal means exclusively in response to occurrence of a commutation signal during a gating time interval commencing upon said change of state of said output signal and terminating upon said lock-out signal being switched from said first to said second state.

Claim 8

In a commutation control apparatus for an inverter circuit comprising first and second load current carrying gate controlled rectifier means connected serially across a source of direct current electric power and first and second commutating gate controlled rectifier means serially connected across said source and commutating circuit means interconnecting the respective junctions of said load current carrying and of said commutating gate controlled rectifier means, said commutation control apparatus being responsive to applied inverter command signals for firing saaid gate controlled rectifier means in predetermined sequence and comprising: a. commutating detection means for providing a commutation signal upon detection of a condition in said inverter circuit indicative of the application of a reverse voltage across said first commutating rectifier means to initiate its turnoff; b. gating means responsive to said commutation signal and adapted to provide at its output a turnoff signal occurring at a turnoff time interval subsequent to the occurrence of said commutation signal; c. lock-out signal means for generating a lock-out signal and responsive to said turnoff signal to switch the level of said lock-out signal from a first to a second state; d. lock-out circuit means for inhibiting firing of said second commutating recrifier means upon firing of said first commutating rectifier until such time as the state of said lock-out signal is switched from said first to said second state; e. pulse generating means for generating a predetermined output signal having a change of state upon expiration of a predetermined first time interval subsequent to firing of said first commutating rectifier means, and f. said gating means being responsive to said output signal and to said lock-out signal for applying said turnoff signal to said lock-out signal means exclusively in response to occurrence of a commutation signal during a gating time interval commencing upon said change of state of said output signal and terminating upon said lock-out signal being switched from said first to said second state.

Claim 9

The commutation control arrangement of claim 6 wherein said lock-out signal means is constructed so as to generate a lock-out signal whose level is switched from said first to a said second state at a predetermined lock-out pulse time interval subsequent to the firing of said first commutating rectifier means, which time interval is at least equal to the minimum safe time period required between the firings of said first and second commutating rectifier means, in the event a turnoff signal is not previously applied to said lock-out signal means during said predetermined lock-out time interval.

Claim 10

The arrangement of claim 7 wherein said lock-out circuit means comprises an input terminal adapted to be connected to a source of bilevel inverter command signals successively having First and second level states, said level states indicative of which of said commutating rectifier means is to be fired, means for coupling command signals of a first level state through a first gating means to fire said first commutating rectifier means and for coupling command signals of a second level state through a second gating means to fire said second commutating rectifier means, and means for coupling said lock-out signal to said first and second gating means to inhibit firing of said second commutating rectifier means subsequent to firing of said first commutating rectifying means until said lock-out signal is switched from said first to said second state.

Claim 11

The arrangement of claim 8 wherein in said inverter circuit said commutating circuit comprises capacitance and inductance means, and wherein first and second sets of serially connected diode rectifier means and resisitance means are connected, respectively, in parallel circuit relationship across said first and second commutating gate controlled rectifier means in reverse polarity therewith, said commutating detection means comprising current sensing means for sensing overcharge current flow in said diode rectifier means when its parallel connected commutating gate controlled rectifier means ceases conduction.

Claim 12

The arrangement of claim 9 wherein said current sensing means comprises transformer means having a primary winding connected in a circuit between the junction of said commutating detection means and a common junction of said first and second sets of diode rectifier means and resistance means.

Claim 13

The arrangement of claim 7 wherein said lock-out signal means comprises pulse generating a lock-out pulse signal switched from said second to said first state substantially coincident with the firing of said first commutating rectifier means and switched from said first to said second state at the termination of said predetermined lock-out pulse time interval or at such earlier time as a turnoff signal is applied to said lock-out signal means, and said lock-out circuit means is constructed to inhibit firing of said second commutating rectifier means during the time interval when said lock-out signal is in said first state.

Claim 14

The arrangement of claim 11 wherein said pulse generating means provides a bilevel output pulse signal switched to one level state substantially coincident with the firing of said first commutating rectifier means and switched to another level state upon expiration of first time interval.

Claim 15

The arrangement of claim 12 wherein said gating means comprises a gating circuit respnsive to said lock-out and output pulse signals and means coupled to the output of said gating circuit for inhibiting generation of a turnoff signal to said lock-out signal means except during the interval commencing upon said output pulse signal being switched to said another level state and terminating upon said lock-out pulse signal being switched from said first to said second state.

Claim 16

In a commutation control apparatus for an inverter circuit including at least one set of two series connected load current carrying gate controlled rectifiers connected across a source of direct current electric power, a respective set of two series connected commutating gate controlled rectifiers of similar polarity connected across said source of electric power and commutating curcuit means interconnecting the junction of said two load current carrying gate controlled rectifiers and the junction of said two commutating gate controlled rectifiers, wherein said commutating control apparatus alternately gates one and the other of said commutating rectifiers responsive to applied inverter command signals and comprises lock-out means responsive to a lock-out pulse for inhibiting premature firing of said other commutating rectifier, lock-out pulse generating means comprising: a. first monostable pulse generating means having a trigger input and an output adapted to provide a first output pulse signal commencIng upon application of a trigger input signal and having a predetermined time duration; b. second monostable pulse generating means having a trigger input and a second input, and an output adapted to provide a lock-out pulse signal commencing upon application of a trigger input signal and terminating upon expiration of a time duration equal at least to the minimum safe time period required between firing of said one and said other cummutating rectifier, unless terminated at such earlier time when a cutoff signal is applied to said second input; c. means for applying a trigger signal to the trigger inputs of said first and second pulse generating means substantially concurrently with the firing of said one commutating rectifier; d. coupling means for coupling the lock-out pulse output of said second pulse generating means to said lock-out means to inhibit firing of said other commutating rectifier during the duration of said lock-out pulse; e. commutating detection means for producing at its output a commutation signal upon the application of a reverse voltage across said one commutating gate controlled rectifier means to initiate its turnoff; f. time delay means adapted to produce a turnoff signal at a predetermined turnoff time interval subsequent to the occurrence of said commutation signal; g. gating means responsive solely during a gating time interval commencing upon termination of said first output pulse signal and ending upon termination of said lock-out pulse signal for applying a signal coincident in time with said turnoff signal, to the second input of said second pulse generating means to terminate said lock-out pulse signal and to enable subsequent firing of said other commutating rectifier.

Claim 17

In a commutation control apparatus for an inverter circuit including at least one set of two series connected load current carrying gate controlled rectifiers connected across a source of direct current electric power, a respective set of two series connected commutating gate controlled rectifiers of similar polarity connected across said source of electric power and commutating curcuit means interconnecting the junction of said two load current carrying gate controlled rectifiers and the junction of said two commutating gate controlled rectifiers, wherein said commutating control apparatus alternately gates one and the other of said commutating rectifiers responsive to applied inverter command signals and comprises lock-out means responsive to a lock-out pulse for inhibiting premature firing of said other commutating rectifier, lock-out pulse generating means comprising: a. first monostable pulse generating means having a trigger input and an output adapted to provide a first output pulse signal commencIng upon application of a trigger input signal and having a predetermined time duration; b. second monostable pulse generating means having a trigger input and a second input, and an output adapted to provide a lock-out pulse signal commencing upon application of a trigger input signal and terminating upon expiration of a time duration equal at least to the minimum safe time period required between firing of said one and said other cummutating rectifier, unless terminated at such earlier time when a cutoff signal is applied to said second input; c. means for applying a trigger signal to the trigger inputs of said first and second pulse generating means substantially concurrently with the firing of said one commutating rectifier; d. coupling means for coupling the lock-out pulse output of said second pulse generating means to said lock-out means to inhibit firing of said other commutating rectifier during the duration of said lock-out pulse; e. commutating detection means for producing at its output a commutation signal upon the application of a reverse voltage across said one commutating gate controlled rectifier means to initiate its turnoff; f. time delay means adapted to produce a turnoff signal at a predetermined turnoff time interval subsequent to the occurrence of said commutation signal; g. gating means responsive solely during a gating time interval commencing upon termination of said first output pulse signal and ending upon termination of said lock-out pulse signal for applying a signal coincident in time with said turnoff signal, to the second input of said second pulse generating means to terminate said lock-out pulse signal and to enable subsequent firing of said other commutating rectifier.

Claim 18

The arrangement of claim 14 wherein said gating means comprises a switching circuit coupled to the outputs of said first and second pulse generating means to produce a switching circuit output signal of a first state during said gating time interval and a signal of a second state during all other time intervals, and inhibit means for inhibiting generation of a turnoff signal when the switching circuit output signal is of a second state.

Claim 19

The arrangement of claim 15 wherein said time delay circuit comprises a resistance-capacitance network connected serially across the output of said commutating detection means and adapted to provide a turnoff voltage signal across the capacitance portion of said network, said inhibit means comprising first unilaterally conducting means coupling said switching circuit output to the circuit junction of said capacitance and resistance portions, said first unilaterally conducting means being poled such that the junction is clamped to a predetermined voltage level during intervals when the switching circuit output is of a second state so as to inhibit generation of a turnoff signal.

Claim 20

The arrangement of claim 16 further comprising second unilaterally conducting means connected to rapidly discharge said capacitance upon generation of said turnoff voltage signal.

Claim 21

The arrangement of claim 17 wherein said junction is coupled to an input of a second switching circuit having an output coupled to the second input of said second pulse generating means, said second switching circuit being biased to switch the state of its output signal coincident with the attainment of a predetermined level of the turnoff voltage signal at said junction.

Claim 22

In combination: an inverter circuit comprising first and second load current carrying gate controlled rectifier means connected serially between a pair of direct current electric power terminals, first and second commutating gate controlled rectifier means of similar polarity serially connected between said terminals, feedback rectifier means connected across said load current carrying gate controlled rectifier means in reversely poled relationship therewith, and oscillatory commutating circuit means interconnecting the respective junctions of said load current carrying and of said commutating gate controlled rectifier means; and commutation control apparatus responsive to applied inverter command signals for firing said gate controlled rectifier means in predetermined sequence said commutation control apparatus including lock-out means effective with the firing of said first commutating rectifier means for inhibiting a premature subsequent firing of said second commutating rectifier means, said lock-out means comprising; a. reverse voltage detecting means for sensing the presence of a discrete signal in said inverter whose presence is indicative of the application of reverse voltage to said first commutating rectifier means; b. timing means responsive to the sensing of said discrete signal and operative to produce a turnoff signal after said reverse voltage condition has continued for a fixed delay interval; and c. control means responsive to an inverter command signal which initiates firing of said first commutating rectifier means for commencing an inhibit period throughout which firing of said second commutating rectifier means is prevented, said control means also being responsive to the production of said turnoff sibnal by said timing means for terminating said inhibit period.

Claim 23

In combination: an inverter circuit comprising first and second load current carrying gate controlled rectifier means connected serially between a pair of direct current electric power terminals, first and second commutating gate controlled rectifier means of similar polarity serially connected between said terminals, feedback rectifier means connected across said load current carrying gate controlled rectifier means in reversely poled relationship therewith, and oscillatory commutating circuit means interconnecting the respective junctions of said load current carrying and of said commutating gate controlled rectifier means; and commutation control apparatus responsive to applied inverter command signals for firing said gate controlled rectifier means in predetermined sequence said commutation control apparatus including lock-out means effective with the firing of said first commutating rectifier means for inhibiting a premature subsequent firing of said second commutating rectifier means, said lock-out means comprising; a. reverse voltage detecting means for sensing the presence of a discrete signal in said inverter whose presence is indicative of the application of reverse voltage to said first commutating rectifier means; b. timing means responsive to the sensing of said discrete signal and operative to produce a turnoff signal after said reverse voltage condition has continued for a fixed delay interval; and c. control means responsive to an inverter command signal which initiates firing of said first commutating rectifier means for commencing an inhibit period throughout which firing of said second commutating rectifier means is prevented, said control means also being responsive to the production of said turnoff sibnal by said timing means for terminating said inhibit period.

Claim 24

The combination of claim 19 wherein said inverter curcuit additionally comprises reset circuit means comprising first and second unilaterally conducting rectifying means which, in series with damping resistance, are connected in parallel circuit, reversely poled relationship with said first and second commutating gate controlled rectifier means, respectively, and wherein said reverse voltage detecting means comprises means for directly sensing curent which flows in said reset circuit means when said first commutating rectifier means in reverse biased.

Claim 25

The combination of claim 20 wherein said means for directly sending current flow comprises sensing means connectd in series circuit intermediate the junction of said first and second commutating rectifier means and a common point in said reset circuit means between said first and second unilaterally conducting rectifying means.

Claim 26

The combination of claim 21 wherein said sensing means comprises the primary winding of a transformer whose secondary winding is coupled to detecting means.

Claim 27

The combination of claim 19 in which said timing means is rapidly reset in response to an interruption of said reverse voltage condition prior to the expiration of said fixed delay interval.

Claim 28

The combination of claim 19 wherein said lock-out means further comprises additional timing means for automatically terminating said inhibit period, if not earlier terminated by said turnoff signal, upon the expiration of a predetermined maximum interval of time after the firing of said first commutating recitifier means is initiated.

Claim 29

The combination of claim 19 wherein said lock-out means further comprises additional timing means for preventing any termination of said inhibit period before the expiration of a predetermined minimum interval of time after the firing of said first commutating rectifier means is initiated.

Claim 30

The combination of claim 25 wherein said additional timing means is effective to render the first-mentioned timing means inoperative for a predetermined first time interval, thereby ensuring that no turnoff signal can be produced before the expiration of said minimum interval of time.

Claim 31

The combination of claim 25 wherein said lock-out means also comprises third timing means for automatically terminating said inhibit period, if not earlier terminated by said turnoff signal, upon the expiration of a predetermined maximum interval of time after the firing of said first commutating rectifier means is initiated.