US3852656A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Inverter fault protection and frequency limiting circuit
Assignee: Motors Liquidation Co
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Filing: 1974-04-19
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Granted: 1974-12-03
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Expires: 1994-04-19
Abstract
Abstract An inverter fault protection and frequency limiting circuit for inverters having controlled rectifier and antiparallel diode pairs is described for preventing short circuits of the inverter power supply and for limiting the operating frequency of the inverter. An inhibit circuit is responsive to controlled rectifier forward blocking voltages and antiparallel diode currents to generate a gate inhibit signal for one of the seriescoupled controlled rectifiers when the other one of the controlled rectifiers is not forward blocking or if the time duration of the current through the antiparallel diode thereof is less than a specified controlled rectifier turn-off time. A frequency limiting circuit is responsive to the gate inhibit signal for limiting the maximum operating frequency of the inverter.
Inventors
- 👤 F Bourbeau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:04
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/505; H02M7/515; H02M7/525
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
288 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current through the diode parallel coupled therewith, the fault protection circuit comprising: means for generating alternating timing logic signals Q and Q, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct and the timing logic signal Q representing the time period during which the second controlled rectifier may conduct; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means coupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) and gating means responsive to the inhibit logic signal I and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I, (3) whereby the inhibit logic signal I is generated to prevent a short circuit fault across the first and second controlled rectifiers.
Claim 2
Dependent Claim
288 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current through the diode parallel coupled therewith, the fault protection circuit comprising: means for generating alternating timing logic signals Q and Q, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct and the timing logic signal Q representing the time period during which the second controlled rectifier may conduct; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means coupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) and gating means responsive to the inhibit logic signal I and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I, (3) whereby the inhibit logic signal I is generated to prevent a short circuit fault across the first and second controlled rectifiers.
Claim 3
Dependent Claim
327 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current through the diode parallel coupled therewith, the fault protection circuit comprising: means for generating variable frequency alternating timing logic signals Q and Q, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct, the timing logic signal Q representing the time period during which the second controlled rectifier may conduct and the frequency of the timing logic signals being equal to a desired operating frequency of the inverter; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means coupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) means responsive to the generation of the inhibit logic signal I for generating a blocking signal IB having a specified time duration: and gating means responsive to the blocking signal IB and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q IB (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q IB, (3) whereby the blocking signal IB is generated to prevent a short circuit fault across the first and second controlled rectifiers.
Claim 4
Dependent Claim
327 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current through the diode parallel coupled therewith, the fault protection circuit comprising: means for generating variable frequency alternating timing logic signals Q and Q, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct, the timing logic signal Q representing the time period during which the second controlled rectifier may conduct and the frequency of the timing logic signals being equal to a desired operating frequency of the inverter; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means coupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) means responsive to the generation of the inhibit logic signal I for generating a blocking signal IB having a specified time duration: and gating means responsive to the blocking signal IB and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q IB (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q IB, (3) whereby the blocking signal IB is generated to prevent a short circuit fault across the first and second controlled rectifiers.
Claim 5
Dependent Claim
387 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current thorugh the diode parallel coupled therewith, the fault protection circuit comprising: means for generating a frequency control voltage; a voltage controlled oscillator coupled to the last mentioned means for generating an output signal having a frequency determined by the magnitude of the frequency control voltage; means coupled to the voltage controlled oscillator for generating alternating timing logic signals Q and Q at a frequency determined by the frequency of the output signal from the voltage controlled oscillator, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct and the timing logic signal Q representing the time period during which the second controlled rectifier may conduct; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means cupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) gating means responsive to the inhibit logic signal I and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I; (3) and frequency limiting means coupled to the voltage controlled oscillator and responsive to the generation of the inhibit logic signal I for limiting the frequency of the output signal from the voltage controlled oscillator, whereby the inhibit logic signal I is generated to prevent a short circuit fault across the first and second controlled rectifiers and for limiting the frequency of operation of the inverter.
Claim 6
Dependent Claim
387 words
A fault protection circuit for an inverter, the inverter including first and second series coupled controlled rectifiers each having a respective oppositely poled diode coupled in parallel therewith and including at least one resonant circuit for commutating each of the controlled rectifiers by driving current thorugh the diode parallel coupled therewith, the fault protection circuit comprising: means for generating a frequency control voltage; a voltage controlled oscillator coupled to the last mentioned means for generating an output signal having a frequency determined by the magnitude of the frequency control voltage; means coupled to the voltage controlled oscillator for generating alternating timing logic signals Q and Q at a frequency determined by the frequency of the output signal from the voltage controlled oscillator, the timing logic signal Q representing the time period during which the first controlled rectifier may conduct and the timing logic signal Q representing the time period during which the second controlled rectifier may conduct; means for sensing current through the diodes and generating a current logic signal D coexistent with sensed current; first voltage sensing means cupled to the first controlled rectifier for generating a voltage logic signal S1 when the first controlled rectifier is forward blocking; second voltage sensing means coupled to the second controlled rectifier for generating a voltage logic signal S2 when the second controlled rectifier is forward blocking; means responsive to the timing logic signals Q and Q, the current logic signal D and the voltage logic signals S1 and S2 for generating an inhibit logic signal I defined by the equation I D + QS1 + QS2; (1) gating means responsive to the inhibit logic signal I and the timing signals Q and Q for gating the first controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I (2) and gating the second controlled rectifier conductive upon the occurrence of a condition defined by the expression Q I; (3) and frequency limiting means coupled to the voltage controlled oscillator and responsive to the generation of the inhibit logic signal I for limiting the frequency of the output signal from the voltage controlled oscillator, whereby the inhibit logic signal I is generated to prevent a short circuit fault across the first and second controlled rectifiers and for limiting the frequency of operation of the inverter.
References Cited (Backward Citations)
US3458797A
Cited
US3686558A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |