US4077044A
Expired / Lapsed
US
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Nonvolatile memory semiconductor device
Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1975-08-28
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Granted: 1978-02-28
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Expires: 1995-08-28
Abstract
Abstract Disclosed is a field-effect transistor device which is capable of storing pieces of analogue information in the form of charge stored in a charge-storing means. A memory device according to this invention comprises, drain and source regions in a semi-conductor substrate, an insulating layer lying on the major surface of the substrate and an elongated resistive gate region lying on the insulating layer between the drain and source regions and having two electrodes provided on the opposite ends of the gate region. When a voltage below the critical voltage of charge injection is applied to one of the electrodes whereas a voltage above the critical voltage and representative of analogue information is applied to the other electrode, the area of charge injection in the charge-storing mechanism of the insulating layer varies with the latter "writing" voltage, thus realizing the storage of analogue information if said area is filled with electric charge. The piece of analogue information thus stored is read in terms of source-to-drain current.
Inventors
- 👤 Yutaka Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:02
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/605; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C27/00; G11C27/005
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
134 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; at least two spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate at least about the channel-forming region; charge-storing means disposed in the insulating layer and at least above the channel-forming region; a gate disposed on the insulating layer above the channel-forming region, the gate comprising an elongated resistive layer; and a first pair of electrodes, one of the electrodes contacting one side of the resistive layer for supplying a voltage varying according to analogue information to be stored in the device and the other electrode contacting the opposite side of the resistive layer.
Claim 2
Dependent Claim
134 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; at least two spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate at least about the channel-forming region; charge-storing means disposed in the insulating layer and at least above the channel-forming region; a gate disposed on the insulating layer above the channel-forming region, the gate comprising an elongated resistive layer; and a first pair of electrodes, one of the electrodes contacting one side of the resistive layer for supplying a voltage varying according to analogue information to be stored in the device and the other electrode contacting the opposite side of the resistive layer.
Claim 3
Dependent Claim
27 words
The device as set forth in claim 1 wherein: the insulating layer is double-laminated; and the charge-storing means is disposed at the interface between the two laminae.
Claim 4
Dependent Claim
35 words
The device as set forth in claim 1, wherein: the charge-storing means is disposed in the insulating layer above a portion of the channel-forming region which is nonadjacent either of the two spaced apart regions.
Claim 5
Dependent Claim
40 words
The device as set forth in claim 1 including: a second pair of electrodes disposed in contact with one of the spaced apart regions, the one of the spaced apart regions exhibiting resistive characteristics between the second pair of electrodes.
Claim 6
Dependent Claim
139 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; at least two spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate at least above the channel-forming region; a charge-storing means disposed in the insulating layer and at least above the channel-forming region; a gate disposed on the insulating layer above the channel-forming region; and a first pair of electrodes disposed in contact with one of the spaced apart regions, the one of the spaced apart regions exhibiting resistive characteristics between the first pair of electrodes, one of the first pair of electrodes functioning for supplying a voltage varying according to analogue information to be stored in the device.
Claim 7
Dependent Claim
139 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; at least two spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate at least above the channel-forming region; a charge-storing means disposed in the insulating layer and at least above the channel-forming region; a gate disposed on the insulating layer above the channel-forming region; and a first pair of electrodes disposed in contact with one of the spaced apart regions, the one of the spaced apart regions exhibiting resistive characteristics between the first pair of electrodes, one of the first pair of electrodes functioning for supplying a voltage varying according to analogue information to be stored in the device.
Claim 8
Dependent Claim
58 words
A device as set forth in claim 5 wherein the gate comprises a resistive layer; and including a second pair of electrodes, one of the second pair of electrodes contacting one end of the gate and the other electrode contacting the opposite end of the gate, both ends of the gate being above the two spaced apart regions.
Claim 9
Dependent Claim
59 words
A device as set forth in claim 5 wherein the gate comprises a resistive layer; and including a second pair of electrodes, one of the second pair of electrodes contacting one end of the gate and the other electrode contacting the opposite end of the gate, both ends of the gate being adjacent to the two spaced apart regions.
Claim 10
Dependent Claim
28 words
The device as set forth in claim 5, wherein: the insulating layer is double-laminated and the charge storing means is disposed at the interface between the two laminae.
Claim 11
Dependent Claim
37 words
The device as set forth in claim 5, wherein: the charge storing means is disposed in the insulating layer above a portion of the channel forming region which is nonadjacent either of the two spaced apart regions.
Claim 12
Dependent Claim
155 words
A nonvolatile semiconductor memory device comprising: the semiconductor substrate of a first conductivity type; first and second spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate above the channel-forming region and adjacent parts of the spaced apart region; a floating gate disposed in the insulating layer above the channel-forming region and the adjacent parts of the spaced apart regions, the floating gate comprising at least two low resistance regions and a high resistance region between the two low resistance regions, the low resistance regions being capacitively coupled to the two spaced apart regions; whereby voltage variations in the two spaced apart regions are coupled to the respective low resistance regions, establishing a potntial gradient across the high resistance region of the floating gate and producing linear resistance characteristics between the two spaced apart regions.
Claim 13
Dependent Claim
155 words
A nonvolatile semiconductor memory device comprising: the semiconductor substrate of a first conductivity type; first and second spaced apart regions in the substrate and of opposite conductivity type to the substrate, the regions defining a channel-forming region in the substrate; an insulating layer disposed on the substrate above the channel-forming region and adjacent parts of the spaced apart region; a floating gate disposed in the insulating layer above the channel-forming region and the adjacent parts of the spaced apart regions, the floating gate comprising at least two low resistance regions and a high resistance region between the two low resistance regions, the low resistance regions being capacitively coupled to the two spaced apart regions; whereby voltage variations in the two spaced apart regions are coupled to the respective low resistance regions, establishing a potntial gradient across the high resistance region of the floating gate and producing linear resistance characteristics between the two spaced apart regions.
Claim 14
Dependent Claim
104 words
The device as set forth in claim 10, wherein the floating gate has portions extending beyond the channel-forming region and coated with an insulating material; and including third and fourth spaced apart regions in the semiconductive substrate, the third and fourth regions being spaced apart from the first and second spaced apart regions, and disposed partly under the extended portions; first means coupled to the third region for supplying a voltage large enough to induce electrical breakdown of the third region; and second means coupled to the fourth region for supplying a compensating voltage variation opposite in direction to that of the first means.
Claim 15
Dependent Claim
73 words
The device as set forth in claim 10 including: an injection region disposed in the semiconductor substrate and of opposite conductivity type to the substrate for injection of minority carriers, the injection region forming a P-N junction with the semiconductor substrate at a distance from the floating gate of several times the diffusion length of the minority carriers in the substrate; and means for forward biasing the P-N junction to erase stored information.
Claim 16
Dependent Claim
24 words
The device as set forth in claim 10, wherein: the floating gate has a structure allowing photons to pass therethrough to the channel-forming region.
Claim 17
Dependent Claim
168 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; first, second and third spaced apart regions in the substrate and of opposite conductivity type to the substrate, the first and second regions defining a first channel-forming region in the substrate, the third spaced apart region and the first channel-forming region defining a second channel-forming region in the substrate; an insulating layer disposed on the substrate at least above the first and second channel-forming regions; charge-storing means disposed in the insulating layer above the second channel-forming region; a first gate disposed on the insulating layer and above the first channel-forming region; a second gate disposed on the insulating layer above the second channel-forming region; the second gate being electrically isolated from the first gate; the second gate comprising a resistive layer; and including two electrodes contacting the resistive layer, one of the electrodes functioning to supply a voltage varying according to analogue information to be stored in the device.
Claim 18
Dependent Claim
168 words
A nonvolatile semiconductor memory device with analogue information storage capability, comprising: a semiconductor substrate of a first conductivity type; first, second and third spaced apart regions in the substrate and of opposite conductivity type to the substrate, the first and second regions defining a first channel-forming region in the substrate, the third spaced apart region and the first channel-forming region defining a second channel-forming region in the substrate; an insulating layer disposed on the substrate at least above the first and second channel-forming regions; charge-storing means disposed in the insulating layer above the second channel-forming region; a first gate disposed on the insulating layer and above the first channel-forming region; a second gate disposed on the insulating layer above the second channel-forming region; the second gate being electrically isolated from the first gate; the second gate comprising a resistive layer; and including two electrodes contacting the resistive layer, one of the electrodes functioning to supply a voltage varying according to analogue information to be stored in the device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-27 | 1981-08-29 | 1982-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-27 | 1985-08-29 | 1986-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-27 | 1989-08-29 | 1990-02-28 | $7700.00 | Window Closed / Lapsed |