Digital microprocessor system with shared decode

Claim 1

An electronic digital processor system of the type having: at least one logic unit having a plurality of command inputs, the logic unit executing functional operations in response to operation commands; memory means for storing instruction words which define the operation of the logic unit and other parts of the system, and addressing means for accessing the memory means; control means including a programmable logic array having first and second sections, said control means receiving instruction words from the addressable memory means and generating therefrom a plurality of operation commands, the operation commands being coupled to said command inputs; timing means for generating timing signals for defining a machine cycle including a first interval during which an address is delivered to said addressing means and including a second interval during which an instruction word is delivered to the control means to generate operation commands; the improvement wherein: the processor system includes a shared decoder having an input and first and second outputs, the first output being connected to the memory means and the second output being connected to said second section of said programmable logic array in said control means, whereby said decoder forms part of said addressing means during the first interval and forms said first section of said programmable logic array during the second interval.