Electronic computers

Claim 2

In an electronic computer the combination comprising: a memory including a first register containing a series of digits to be read out and a second register containing symbols to be read out in conjunction with the digits; a shift register; means for connecting said shift register to one of the register, the information in said one register passing through said shift register and being re-entered into said one register, each pass through the shift register causing the information to be displaced by one digit with respect to the information in the other register, detecting means for detecting alignment of the information in said first register with the information in said second register, means responsive to said detecting means for discontinuing the passing through the shift register upon detecting said alignment; and means for selectively reading the information out of said two registers, the digits being serially read-out of said first register unless a symbol is found in a stage of the second register which corresponds to the stage of the first register about to be read-out, said symbol being read-out and placed in series with the digits which had been previously read out of the first register.

Claim 3

The combination according to claim 1 including means for placing a tag bit in the digit location of the first register corresponding to the maximum number of decimals desired and means for placing a tag bit in the digit location of the second register, the tag bits in the first and second registers being separated by a number of digit locations corresponding to the maximum number of digits to be read-out.

Claim 4

In an electronic computer, apparatus for separating the whole number portion and the decimal portion of a number made up of a plurality of multibit digits into separate registers, a predetermined bit place of the least significant digit of the whole number portion being used to indicate the presence of the decimal point, comprising: a first and a second storage register, the first containing the number to be separated, the second to receive the decimal portion of the separated number; first, second and third gates; a first and a second shift register, each able to contain the bits of a digit, the output of the first shift register being connected to the input of the second shift register and the first storage register connected to the input of the first shift register and the output of the second shift register being connected to the input of the first storage register by means of Said first gate, the output of the first shift register being connected to the input of the first storage register by means of said second gate and being connected to the input of the second storage register by means of said third gate; means for detecting the passing through of the first shift register of the digit containing the decimal point; means for passing the digits to the right of the decimal point through the first shift register and the second gate and back to the first storage register; means responsive to the passing through of the first shift register of the digit containing the decimal point for passing said digit through the third gate to the second storage register; means for blocking the second gate when the digit with the decimal point is passing through the third gate except when the decimal point bit leaves the first shift register; and means for selectively enabling the first gate to pass a selected bit of the digit present in the second shift register representing the sign of the decimal portion back to said first storage register when the decimal point digit is in the first shift register.

Claim 5

In an electronic computer, apparatus for separating the whole number portion and the decimal portion of a number made up of a plurality of multibit digits into separate registers, a predetermined bit place of the least significant digit of the whole number portion being used to indicate the presence of the decimal point, comprising: a first and a second storage register, the first containing the number to be separated, the second to receive the decimal portion of the separated number; first, second and third gates; a first and a second shift register, each able to contain the bits of a digit, the output of the first shift register being connected to the input of the second shift register and the first storage register connected to the input of the first shift register and the output of the second shift register being connected to the input of the first storage register by means of Said first gate, the output of the first shift register being connected to the input of the first storage register by means of said second gate and being connected to the input of the second storage register by means of said third gate; means for detecting the passing through of the first shift register of the digit containing the decimal point; means for passing the digits to the right of the decimal point through the first shift register and the second gate and back to the first storage register; means responsive to the passing through of the first shift register of the digit containing the decimal point for passing said digit through the third gate to the second storage register; means for blocking the second gate when the digit with the decimal point is passing through the third gate except when the decimal point bit leaves the first shift register; and means for selectively enabling the first gate to pass a selected bit of the digit present in the second shift register representing the sign of the decimal portion back to said first storage register when the decimal point digit is in the first shift register.

Claim 6

In an electronic computer, means for limiting the number of digits of a number to be used in calculations comprising: an operation register having a predetermined number of digit locations and containing said number to be used; counting means capable of counting up to said predetermined number; means for entering into the counting means a number indicating the maximum number of digits to be maintained for said number to be used; means for cyclically reading in series the digits of said number to be used in the operation register from the less to the most significant digits; means for re-entering the digits so read back into the register; means controlled by said reading means for locating the most significant digit of the number to be used; means responsive to said locating means for causing said counting means to count each digit location of the operation register following the most significant digit departing from said entered maximum number; and means controlled by said responsive means for disabling said means for re-entering until said counting means fills, thereby erasing digits from the operating register; the maximum count of said counting means being equal to said maximum number of digits plus the number of erased digit locations.

Claim 7

In an electronic computer, means for limiting the number of digits of a number to be used in calculations comprising: an operation register having a predetermined number of digit locations and containing said number to be used; counting means capable of counting up to said predetermined number; means for entering into the counting means a number indicating the maximum number of digits to be maintained for said number to be used; means for cyclically reading in series the digits of said number to be used in the operation register from the less to the most significant digits; means for re-entering the digits so read back into the register; means controlled by said reading means for locating the most significant digit of the number to be used; means responsive to said locating means for causing said counting means to count each digit location of the operation register following the most significant digit departing from said entered maximum number; and means controlled by said responsive means for disabling said means for re-entering until said counting means fills, thereby erasing digits from the operating register; the maximum count of said counting means being equal to said maximum number of digits plus the number of erased digit locations.