Patent US4071778A successfully refreshed from Google Patents.
US4071778A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog operation circuit using a multi-collector lateral transistor
Assignee: Hitachi Ltd
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Filing: 1976-07-13
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Granted: 1978-01-31
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Expires: 1996-07-13
Abstract
Abstract An analog operation circuit using a lateral transistor element having an emitter region, a base region disposed adjacent to and around the emitter region, a first collector region disposed in the base region adjacent to the emitter region through part of the base region, and a second collector region disposed outside the first collector region to surround the outside of the first collector region through part of the base region. The circuit comprises a first input means for applying a first input signal to the base of the transistor element, a second input means for applying a second input signal to the first collector of the transistor element, an output means derived from the second collector of the transistor element, and a bias means connected to the first collector for applying such a bias voltage that makes the transistor element operate in the saturation region. This analog operation circuit is afforded with an analog operation function by the utilization of the characteristics of such a lateral transistor, and has a simple circuit structure and a reduced number of circuit elements.
Inventors
- 👤 Yoshiyuki Nakagomi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:44
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
167 words
An analog operation circuit comprising: a lateral transistor element having an emitter region having an emitter electrode, a base region having a base electrode, a first collector region having a first collector electrode and formed between said emitter region and part of said base region, and a second collector region having a second collector electrode and formed outside the first collector region between the outside of said first collector region and part of said base region, said emitter electrode being supplied with an operating voltage; means for applying a first input signal to the base electrode of said lateral transistor; means for applying a second input signal to the first collector electrode of said lateral transistor; output means for deriving an output signal from the second collector electrode of said lateral transistor; and biasing means for biasing the lateral transistor element using said first collector electrode as its sole collector to operatein the transition region between the active region and the saturation region of its operating characteristics.
Claim 2
Dependent Claim
167 words
An analog operation circuit comprising: a lateral transistor element having an emitter region having an emitter electrode, a base region having a base electrode, a first collector region having a first collector electrode and formed between said emitter region and part of said base region, and a second collector region having a second collector electrode and formed outside the first collector region between the outside of said first collector region and part of said base region, said emitter electrode being supplied with an operating voltage; means for applying a first input signal to the base electrode of said lateral transistor; means for applying a second input signal to the first collector electrode of said lateral transistor; output means for deriving an output signal from the second collector electrode of said lateral transistor; and biasing means for biasing the lateral transistor element using said first collector electrode as its sole collector to operatein the transition region between the active region and the saturation region of its operating characteristics.
Claim 3
Dependent Claim
53 words
An analog operation circuit according to claim 1, in which said biasing means includes a transistor means connected between said second input signal applying means and a reference potential and having a control electrode supplied with the second input signal to provide a bias voltage in accordance with the applied second input signal.
Claim 4
Dependent Claim
42 words
An analog operation circuit according to claim 1, further comprising an input resistor connected to the base electrode of said lateral transistor element and an output load connected between the second collector electrode of said lateral transistor element and a reference potential.
Claim 5
Dependent Claim
155 words
An analog operational circuit formed in a semiconductor substrate comprising: a multi-collector lateral transistor having an emitter region, a base region, at least two separate collector regions disposed between said emitter region and said base region so as to surround one collector region nearer to the emitter region by the other collector region, said emitter region being supplied with an operating voltage; input means connected to the base region of said transistor for supplying a first input signal thereto; bias voltage means connected to said one collector region of the transistor for applying a bias voltage depending upon a second input signal thereto; and output means connected to said the other collector region of the transistor for providing an output signal; the bias voltage being such that a transistor comprising said one collector region as its sole collector may operate in a transition region between an active and a saturation region of its operation characteristics.
Claim 6
Dependent Claim
155 words
An analog operational circuit formed in a semiconductor substrate comprising: a multi-collector lateral transistor having an emitter region, a base region, at least two separate collector regions disposed between said emitter region and said base region so as to surround one collector region nearer to the emitter region by the other collector region, said emitter region being supplied with an operating voltage; input means connected to the base region of said transistor for supplying a first input signal thereto; bias voltage means connected to said one collector region of the transistor for applying a bias voltage depending upon a second input signal thereto; and output means connected to said the other collector region of the transistor for providing an output signal; the bias voltage being such that a transistor comprising said one collector region as its sole collector may operate in a transition region between an active and a saturation region of its operation characteristics.
Claim 7
Dependent Claim
29 words
The analog operational circuit according to claim 4, in which said two separate collector regions are of circular or ring shape and are formed concentrically of said emitter region.
Claim 8
Dependent Claim
31 words
The analog operational circuit according to claim 4, in which said other collector region has a segmented circular form, said segmented regions constituting a plurality of output collectors is said transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-30 | 1981-08-01 | 1982-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-30 | 1985-08-01 | 1986-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-30 | 1989-08-01 | 1990-01-31 | $7700.00 | Window Closed / Lapsed |