US3914622A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latch circuit with noise suppression
Assignee: Fairchild Semiconductor Corp
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Filing: 1974-02-08
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Granted: 1975-10-21
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Expires: 1994-02-08
Abstract
Abstract A latch circuit with noise suppression which comprises a first transistor having at least two collector regions, one of which is coupled as a feedback to the base region of the first transistor, and the second of which is coupled to the base region of a second transistor. The collector region of the second transistor is coupled to the base region of the first transistor, the emitter region of the first transistor is coupled to a voltage source, and the emitter region of the second transistor is coupled to a reference, or ground potential. Miller effect capacitance is employed at the base of the second transistor for suppressing noise pulses produced by the voltage supply to prevent turning on the latch circuit erroneously.
Inventors
- 👤 Donald E Pezzolo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:24
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/01; H03K3/013; H10; H10D; H10D84/00; H10D84/60; H10D84/63
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
143 words
Circuits which comprises: a. a first transistor of a first conductivity type having at least two collector regions, a base region, and an emitter region coupled to a voltage source; b. a second transistor of a conductivity type opposite from that of said first transistor having a base region, an emitter region coupled to a reference potential, and a collector region coupled to said base region of said first transistor; c. a resistive means coupling said base region of said second transistor to a first of said at least two collector regions; d. capacitive means coupling said base region of said second transistor to said reference potential, said resistive means and said capacitive means co-act to suppress the amplitude of voltage transients; and, e. means coupling a second one of said at least two collector regions to said base region of said transistor.
Claim 2
Dependent Claim
143 words
Circuits which comprises: a. a first transistor of a first conductivity type having at least two collector regions, a base region, and an emitter region coupled to a voltage source; b. a second transistor of a conductivity type opposite from that of said first transistor having a base region, an emitter region coupled to a reference potential, and a collector region coupled to said base region of said first transistor; c. a resistive means coupling said base region of said second transistor to a first of said at least two collector regions; d. capacitive means coupling said base region of said second transistor to said reference potential, said resistive means and said capacitive means co-act to suppress the amplitude of voltage transients; and, e. means coupling a second one of said at least two collector regions to said base region of said transistor.
Claim 3
Dependent Claim
53 words
A circuit as defined in claim 1, including resistive means coupled between said base region of said first transistor and said collector region of said second transistor for increasing the voltage gain of said second transistor so that the capacitance of said capacitive means increases, thereby improving the suppression of voltage amplitude transients.
Claim 4
Dependent Claim
35 words
A circuit as defined in claim 1 wherein the size of said first collector is larger than the size of said second collector, and the actual closed-loop beta of said first transistor is defined as:
Claim 5
Dependent Claim
28 words
A circuit as defined in claim 1 further including a resistive element coupling the base region of said first transistor to the emitter region of said first transistor.
Claim 6
Dependent Claim
19 words
A circuit as defined in claim 4 further including a resistive element coupled in parallel with said capacitive means.
Claim 7
Dependent Claim
23 words
A circuit as defined in claim 1 wherein the input of said circuit is coupled to the base region of said second transistor.
Claim 8
Dependent Claim
38 words
A circuit as defined in claim 1 wherein a resistive element is coupled between the emitter region of said second transistor and said reference potential for providing a constant current load independent of variations in said voltage source.
Claim 9
Dependent Claim
36 words
A circuit as defined in claim 1 wherein a resistive element is coupled between the collector region of said second transistor and the base region of said first transistor for increasing the gain of said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-20 | 1979-04-21 | 1979-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-20 | 1983-04-21 | 1983-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-20 | 1987-04-21 | 1987-10-21 | $7700.00 | Window Closed / Lapsed |