US3818462A — Noise immune i.c. memory cell

Claim 1

Independent Claim 337 words

An integrated circuit bistable memory cell comprised of: a. a first and second current-source-pair of transistors; b. a first coupling resistor connecting the bases of said first pair to the open collector of said second pair, in conventional bistable circuit fashion; c. a second coupling resistor connecting the bases of said second pair to the open collector of said first pair, in conventional bistable circuit fashion; d. a third current-source-pair wherein the collector of the active transistor is connected to said collector of said first pair; e. a fourth current-source-pair wherein the collector of the active transistor is connected to said collector of said second pair; f. a ground connection being made to all transistor emitters of said pairs; g. two terminals for connecting a d.c. voltage power supply to said integrated circuit, one terminal of which connects to said ground connection; h. a constant current active load comprised of one or more transistors and a reference resistor, being connected between the other terminal for said power supply and the open transistor collectors of said first and third pairs; and i. another constant current active load comprised of one or more transistors and a reference resistor, being connected between said other terminal of said power supply and the open collectors of said second and fourth pairs; wherein a one stable operating state consists in said first pair conducting and said second pair being cut off; another stable operating state consists in said second pair conducting and said first pair being cut off; and a signal current may be applied to the bases of said fourth pair causing said memory cell to switch from said one stable state to said other stable state when said signal amplitude exceeds the characteristic circuit threshold value of said cell, said threshold value being substantially proportional to said power supply voltage, and similarly a signal current may be applied to the bases of said third pair causing said memory cell to switch from said other stable state to said one stable state.

Claim 2

Dependent Claim 337 words

An integrated circuit bistable memory cell comprised of: a. a first and second current-source-pair of transistors; b. a first coupling resistor connecting the bases of said first pair to the open collector of said second pair, in conventional bistable circuit fashion; c. a second coupling resistor connecting the bases of said second pair to the open collector of said first pair, in conventional bistable circuit fashion; d. a third current-source-pair wherein the collector of the active transistor is connected to said collector of said first pair; e. a fourth current-source-pair wherein the collector of the active transistor is connected to said collector of said second pair; f. a ground connection being made to all transistor emitters of said pairs; g. two terminals for connecting a d.c. voltage power supply to said integrated circuit, one terminal of which connects to said ground connection; h. a constant current active load comprised of one or more transistors and a reference resistor, being connected between the other terminal for said power supply and the open transistor collectors of said first and third pairs; and i. another constant current active load comprised of one or more transistors and a reference resistor, being connected between said other terminal of said power supply and the open collectors of said second and fourth pairs; wherein a one stable operating state consists in said first pair conducting and said second pair being cut off; another stable operating state consists in said second pair conducting and said first pair being cut off; and a signal current may be applied to the bases of said fourth pair causing said memory cell to switch from said one stable state to said other stable state when said signal amplitude exceeds the characteristic circuit threshold value of said cell, said threshold value being substantially proportional to said power supply voltage, and similarly a signal current may be applied to the bases of said third pair causing said memory cell to switch from said other stable state to said one stable state.

Claim 3

Dependent Claim 309 words

The memory cell of claim 1 having: a. a first redundant holding circuit comprised of a normal signal inverting stage whose emitter is grounded and whose output is connected to the bases of said first pair; b. a second redundant holding circuit comprised of an emitter follower stage whose output is connected to the bases of said second pair and whose collector is grounded such that for voltages or impedances above a certain level at the input of said second holding circuit, said cell remains in or switches to said other stable operating state; c. a buffer stage comprised of an emitter follower whose output is tied to the input of said first redundant holding circuit, such that for voltages or impedances below a certain level at the input of said buffer, said cell remains in or changes to sAid one stable operating state; d. a first input terminal connected to said input of said buffer stage and said input of said second redundant holding circuit, such that a first external switch may be connected between said first input terminal and circuit ground, and said cell always assumes said other stable operating state if said first switch is open and contrarily said cell switches to said one stable state if said first switch is closed; e. a second input terminal; and f. a disabling circuit comprised of a network of diodes connecting between each of said redundant holding circuits and said second input terminal, such that a second external switch may be connected between said second input terminal and circuit ground, and if said second switch is closed, said holding circuits block out said input signals and noise to said cell, and further such that for either condition of said second switch, any noise introduced in said disabling circuit cannot effect a change in said state of said cell.

Claim 4

Dependent Claim 77 words

A memory cell of claim 2 having a logic circuit connected to said second input terminal, to said open collector of said first or second pair, and to said output of said buffer; wherein said output of said logic circuit may be connected to an alarm device and said logic output voltage level is a function of the positions of said first and second external switches and the time sequence by which they are opened and closed.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1977-06-17	1977-12-17	1978-06-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1981-06-17	1981-12-17	1982-06-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1985-06-17	1985-12-17	1986-06-18	$7700.00	Window Closed / Lapsed

Noise immune i.c. memory cell

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag