Discrete and integrated-type circuit

Claim 2

A latching-type device having first and second terminals and being characterized by a substantial differential between its turn-on and holding current levels, said device comprising the combination of a pair of regeneratively connected transistors coupled between said terminals, and switch means connected between one of said transistors and said second terminal for providing a path to bypass current flowing from said first terminal and through said one transistor around the other of said transistors to said second terminal, said switch means having means including a resistor responsive to the current level so as to provide a relatively high impedance bypass path at said turnon current level and a relatively low impedance bypass path at said holding current level.

Claim 3

The latching-type device of claim 1 comprised by a single integrated circuit which includes separation isolation islands for said switch means and said transistors, respectively.

Claim 4

The latching-type device of claim 2 wherein said transistors are complementary transistors each of which includes a base, collector, and emitter, each of said transistors having its base connected to the collector of the other and its emitter connected to a respective one of said terminals.

Claim 5

The latching-type device of claim 3 wherein the isolation island for said transistors comprises a layer of N-type semiconductor material, three laterally spaced deposits of P-type semiconductor material overlying and extending a predetermined distance into said layer of N-type semiconductor material, and a deposit of N+-type semiconductor material overlying and extending a predetermined distance into the centrally located one of said P-type deposits, whereby the outer two of said P-type deposits define the emitter of a PNP transistor, the N+-type deposit defines the emitter of a NPN transistor, the centrally located P-type deposit defines the collector of the PNP transistor and the base of the NPN transistor, and the N-type layer defines the base of the PNP transistor and the collector of the NPN transistor.

Claim 6

The latching-type device of claim 4 further including a further deposit of P-type semiconductor material encompassing the laterally spaced P-type deposits and being connected to the N-type layer for collecting spurious current flow from the outer two of the P-type deposits and returning it to the base and collector of the PNP and NPN transistors, respectively.

Claim 7

The latching-type device of claim 5 wherein said N-type layer is an epitaxial layer grown on a substrate of P-type semiconductor material, and said deposits are diffusions.

Claim 8

A semiconductor latching-type device having anode, cathode and gate terminals and being characterized by having a relatively low anode current turn-on level and a relatively high anode current holding level, said device comprising the combination of a pair of regeneratively connected complementary transistors coupled between said anode and cathode terminals, and bypass means connected between one of said transistors and said cathode terminal for providing a path to bypass anode current around the other of said transistors, said bypass means having means including a resistor responsive to the level of said anode Current so that said path has an impedance which drops from a relatively high level to a relatively low level as said anode current increases from said turn-on level to said holding current level.

Claim 9

A semiconductor latching-type device having anode, cathode and gate terminals and being characterized by having a relatively low anode current turn-on level and a relatively high anode current holding level, said device comprising the combination of a pair of regeneratively connected complementary transistors coupled between said anode and cathode terminals, and bypass means connected between one of said transistors and said cathode terminal for providing a path to bypass anode current around the other of said transistors, said bypass means having means including a resistor responsive to the level of said anode Current so that said path has an impedance which drops from a relatively high level to a relatively low level as said anode current increases from said turn-on level to said holding current level.

Claim 10

The latching-type device of claim 7 wherein one of said transistors is a PNP-type and the other is a NPN-type, each of said transistors includes a base, emitter and collector, the base of each transistor is connected to the collector of the other, and the emitters of the PNP and NPN transistors are respectively connected to said anode and cathode, said integrated circuit further including means interposed between said transistors and said bypass means for electrically isolating them from each other.

Claim 11

The latching-type device of claim 8 wherein said bypass means includes another NPN transistor having a base, collector and emitter, said other NPN transistor having its base and collector connected to the collector of said PNP transistor and its emitter connected to the emitter of the first mentioned NPN transistor whereby the base-emitter and collector-emitter circuits of said other NPN transistor are in parallel with the base-emitter circuit of said first NPN transistor, and further including a resistor connected in series with the base of said other NPN transistor so that the collector-emitter circuit of said other NPN transistor comprises a relatively high impedance bypass path when said anode current is at said turn-on level and a relatively low impedance bypass path when said anode current is at said holding level.

Claim 12

The latching-type device of claim 9 wherein said PNP transistor and said first NPN transistor are defined by a layer of N-type semiconductor material, three laterally spaced deposits of P-type semiconductor material overlying said layer, and a deposit of N+-type semiconductor material overlying the middle one of said P-type deposits, and further including another deposit of P-type semiconductor material overlying said layer and encompassing said laterally spaced P-type deposits to define an additional collector for said PNP transistor.

Claim 13

The latching-type device of claim 10 wherein said other deposit of P-type semiconductor material is electrically connected to said N-type layer.

Claim 14

The latching-type device of claim 9 wherein said resistor is a pinched base resistor whereby the amount of current bypassed through the collector-emitter circuit of said other NPN transistor is substantially independent of its beta versus base current characteristics.

Claim 15

An integrated semiconductor thyristor having anode, cathode and gate terminals, said thyristor comprising a first isolation island including a pair of complementary, regeneratively connected transistors extending between said anode and cathode terminals and having a common connection to said gate terminal, and means for providing a path to bypass current flowing from said anode terminal and through one of said transistors around the other of said transistors to said cathode terminal, said means including a second isolation island defining a further transistor and means including a resistor for externally coupling said further transistor to said complementary transistors, whereby said bypass path has an impedance which decreases from a relatively high level to a relatively low level as said current flow increases such that said thyristor has a turn-on current level and a higher holding current level separated by a substantial differential.

Claim 16

An integrated semiconductor thyristor having anode, cathode and gate terminals, said thyristor comprising a first isolation island including a pair of complementary, regeneratively connected transistors extending between said anode and cathode terminals and having a common connection to said gate terminal, and means for providing a path to bypass current flowing from said anode terminal and through one of said transistors around the other of said transistors to said cathode terminal, said means including a second isolation island defining a further transistor and means including a resistor for externally coupling said further transistor to said complementary transistors, whereby said bypass path has an impedance which decreases from a relatively high level to a relatively low level as said current flow increases such that said thyristor has a turn-on current level and a higher holding current level separated by a substantial differential.

Claim 17

The thyristor of claim 13 wherein said first isolation island comprises a first layer of N-type semiconductor material supporting laterally spaced deposits of P-type semiconductor material and a first deposit of N+-type semiconductor material overlying one of said P-type deposits, whereby said complementary transistors are a PNP transistor and a NPN transistor with the first N+-type deposit defining an emitter of said NPN transistor, said one P-type deposit defining a base of saId NPN transistor and a collector of said PNP transistor, the first N-type layer defining a collector of said NPN transistor and a base of said PNP transistor, and another of said P-type deposits defining an emitter of said PNP transistor; said anode, cathode, and gate terminals are respectively brought out from said other P-type deposit, said first N+-type deposit and said first N-type layer; said second isolation island includes a second layer of N-type semiconductor material supporting a further deposit of P-type semiconductor material underlying a second deposit of N+-type semiconductor material, whereby said further transistor is a NPN transistor having a base, collector and emitter respectively defined by said further P-type deposit, said second N-type layer and said second N+-type deposit; said further P-type deposit and said second N-type layer are externally coupled to said one P-type deposit; and said second N+-type deposit is externally coupled to said first N+-type deposit; said thyristor further including a predetermined resistance interposed between said further P-type deposit and said one P-type deposit, whereby the conductivity of said further NPN transistor is controlled to increase as said current flow increases from said turn-on current level to said holding current level to thereby decrease the impedance of said bypass path.

Claim 18

The thyristor of claim 14 wherein said resistance is provided by a pinched base resistor, whereby the impedance of said bypass path is substantially independent of the beta versus base current characteristics of said further NPN transistor.

Claim 19

A latching type solid state assembly having anode, cathode and gate terminals comprising in combination first and second transistors connected between said terminals with the output circuit of one transistor being connected in series with the input circuit of the other so as to provide regenerative action, the gate terminal being connected to one of the transistor input circuits for supplying gate current to such input circuit to initiate flow of load current between the anode and cathode terminals at a low turn-on level, an auxiliary transistor having its output circuit connected in parallel with the input circuit of the second transistor in current by-passing relationship and having its input circuit coupled to the output circuit of the first transistor, and a resistor interposed in the coupled circuit, the value of the resistor being such that the auxiliary transistor is substantially open circuited in the face of low turn-on current but progressively conducting at higher values of load current so as to bypass a progressively greater amount of current around the input circuit of the second transistor so that the holding load current required to hold the first and second transistors in conduction in absence of gate current is many times greater than the holding load current which would be required in the absence of the auxiliary transistor to provide a substantial differential between the turn-on and holding current levels thereby to facilitate turn-off.

Claim 20

A latching type solid state assembly having anode, cathode and gate terminals comprising in combination first and second transistors connected between said terminals with the output circuit of one transistor being connected in series with the input circuit of the other so as to provide regenerative action, the gate terminal being connected to one of the transistor input circuits for supplying gate current to such input circuit to initiate flow of load current between the anode and cathode terminals at a low turn-on level, an auxiliary transistor having its output circuit connected in parallel with the input circuit of the second transistor in current by-passing relationship and having its input circuit coupled to the output circuit of the first transistor, and a resistor interposed in the coupled circuit, the value of the resistor being such that the auxiliary transistor is substantially open circuited in the face of low turn-on current but progressively conducting at higher values of load current so as to bypass a progressively greater amount of current around the input circuit of the second transistor so that the holding load current required to hold the first and second transistors in conduction in absence of gate current is many times greater than the holding load current which would be required in the absence of the auxiliary transistor to provide a substantial differential between the turn-on and holding current levels thereby to facilitate turn-off.

Claim 21

The latching type solid state assembly of claim 16 in which all three of the transistors are included in a single integrated circuit.

Claim 22

The latching type solid state assembly of claim 16 wherein the first and second transistors are complementary with each having its base connected to the collector of the other and its emitter connected to a respective one of the terminals and in which the resistor is connected to the collector of the first transistor.