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US4070653A
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Random access memory cell with ion implanted resistor element
Assignee: Texas Instruments Inc
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Filing: 1976-06-29
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Granted: 1978-01-24
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Expires: 1996-06-29
Abstract
Abstract A self-refresh MOS RAM cell uses a resistor element made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor element is beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. The cell employs two transistors and a gated capacitor, connected in a manner such that a stored "1" switches the implanted resistor to a high impedance state, while a stored "0" maintains the resistor in a relatively low resistance state.
Inventors
- 👤 G. R. Mohan Rao
- 👤 Gerald R. Rogers
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
135 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, an intermittent voltage source coupled to the gate of the second transistor at a second node, and an impedance element connecting the first node to the second node, the impedance element exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high.
Claim 2
Dependent Claim
135 words
A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, an intermittent voltage source coupled to the gate of the second transistor at a second node, and an impedance element connecting the first node to the second node, the impedance element exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high.
Claim 3
Dependent Claim
19 words
A circuit according to claim 1 wherein a gated capacitor couples the intermittant voltage source to the second node.
Claim 4
Dependent Claim
27 words
A circuit according to claim 1 wherein the impedance element is a region within the semiconductor material formed by ion implant and having a low impurity concentration.
Claim 5
Dependent Claim
22 words
A circuit according to claim 3 wherein the region which forms the impedance element is buried beneath a thick thermal oxide layer.
Claim 6
Dependent Claim
50 words
A circuit according to claim 4 wherein a gated capacitor couples the intermittant voltage source to the second node, the gate capacitor including a semiconductor region connected to the second node and functioning to invert and provide a large capacitance area when the voltage on the second node is high.
Claim 7
Dependent Claim
88 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device connecting the storage node to the voltage supply, resistance means connecting the storage node to a refresh node, the refresh node being connected to the control element of the second switching device, and means for applying an intermittent voltage to the refresh node.
Claim 8
Dependent Claim
88 words
A storage cell comprising an address line, a data line, a storage node, a first controlled switching device having a current path connecting the data line to the storage node and being controlled by the address line, a voltage supply, a second controlled switching device connecting the storage node to the voltage supply, resistance means connecting the storage node to a refresh node, the refresh node being connected to the control element of the second switching device, and means for applying an intermittent voltage to the refresh node.
Claim 9
Dependent Claim
18 words
A storage cell according to claim 6 wherein the means for applying an intermittent voltage include capacitance means.
Claim 10
Dependent Claim
36 words
A storage cell according to claim 6 wherein the resistance means exhibits a large change in resistance when the voltage at its terminals changes from near reference potential to near the value of the voltage supply.
Claim 11
Dependent Claim
25 words
A storage cell according to claim 6 wherein the controlled switching devices are MOS transistors and the resistance means is a junction-type field effect transistor.
Claim 12
Dependent Claim
35 words
A storage cell according to claim 6 wherein the cell is within a semiconductor integrated circuit and the resistance means is formed by an elongated region in the semiconductor material of low net impurity concentration.
Claim 13
Dependent Claim
21 words
A storage cell according to claim 10 wherein the cutoff voltage of the resistance means is about 5 to 7 volts.
Claim 14
Dependent Claim
23 words
A storage cell according to claim 10 wherein the switching devices are MOS transistors and the resistance means resembles a junction field-effect transistor.
Claim 15
Dependent Claim
21 words
A storage cell according to claim 12 wherein the resistance means comprises an ion-implanted region beneath a thick, thermally-grown oxide layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-23 | 1981-07-25 | 1982-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-23 | 1985-07-25 | 1986-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-23 | 1989-07-25 | 1990-01-24 | $7700.00 | Window Closed / Lapsed |