Digital carrier wave detect circuitry

Claim 2

Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising input terminals at which at least the train of transitions of a digital data modulated carrier wave signal is applied, output terminals at which a signal level indicative of said carrier wave detected is presented, inputting terminals at which a clock pulse train is applied having a number of impulses greater than the number of said transitions of said wave for a given period of time, a counting circuit having reset, input and output terminals, And gating circuitry connected to said output terminals of said counting circuit and having output terminals at which electric levels are delivered for a plurality of predetermined counts corresponding to the appearance of said transitions in said modulated wave with respect to said impulses of said clock pulse train, control circuitry connected to said input terminals, to said inputting terminals and to said reset and input terminals of said counting circuit for gating said clock impulses to said counting circuit for counting clock impulses between transitions of said modulated wave, and output circuitry coupled between said AND gating circuitry output terminals and said signal level output terminals and responsive to a predetermined count for indicating properly spaced transitions.

Claim 3

Digital carrier wave detect circuitry as defined in claim 1 and wherein said output circuitry comprises a latching flip-flop circuit having set, reset, and complementary output terminals, and said AND gating circuitry comprises at least two AND gating circuits having output leads individually connected to said set and reset terminals of said flip-flop circuit.

Claim 4

Digital carrier wave detect circuitry as defined in claim 2 and wherein said AND gating circuitry comprises at least two additional AND gating circuits having output leads individually connected to said set and reset terminals of said flip-flop circuit, whereby one of two different counts is effective to set said flip-flop circuit and one of two other different counts is effective to reset said flip-flop circuit.

Claim 5

Digital carrier wave detect circuitry as defined in claim 3 and wherein an OR gating circuit is interposed between the set terminal of said flip-flop circuit and the two AND gating circuits connected thereto, and another OR gating circuit is interposed between the reset terminals of said flip-flop circuit and the other two AND gating circuits.

Claim 6

Digital carrier wave detect circuitry as defined in claim 4 and wherein said output circuitry further comprises a bidirectional counting circuit having output terminals connected to said signal level output terminals, up-count terminals connected to the erect output terminals of said latching flip-flop circuit, down-count terminals connected to the complementary output terminals of said flip-flop circuit and counting pulse input circuitry, and said control circuitry further comprises circuitry connected between said inputting terminals and said counting pulse input circuity for applying clocking impulses to said bidirectional counter under control of said flip-flop circuit.

Claim 7

Digital carrier wave detect circuitry as defined in claim 5 and wherein said bidirectional counting circuit has one auxiliary output terminal delivering an output corresponding to a condition of not all binary ones and another auxiliary output terminal delivering an output corresponding to a condition of not all binary zeros, an AND gating circuit having input and output leads interposed between said up-count terminal and said flip-flop circuit and having another input lead connected to said one auxiliary output terminal, another AND gating circuit having input and output leads interposed between said down-count terminal and the other output terminal of said flip-flop circuit and having another input lead connected to said other auxiliary output terminal.

Claim 8

Digital carrier wave detect circuitry as defined in claim 1 and wherein said control circuitry comprises an exclusive OR (XOR) gating circuit having an input terminal connected to one of said input terminals, another input terminal, and an output terminal, a delay circuit connected between said input terminals and said other input terminal of said XOR gating circuit, a latching flip-flop circuit having a set terminal connected to said output lead of said XOR gating circuit, a reset terminal and an output terminal, at least two concatenated edge triggered flip-flop circuits each having data, clock and complementary output terminals with the data terminal of the first of said concatenated flip-flop circuit connected to the output terminal of said latching flip-flop circuit and the interconnection of the first and second concatenated flip-flop circuits also connected to the reset terminal of said latching flip-flop circuit, and the clock terminals of all of said concatenated flip-flop circuits connected to said inputting terminals, an AND gating circuit having one input terminal connected to the output terminal of the final flip-flop circuit, another input terminal connected to said inputting terminals and having an output lead connected to the reset terminal of said counting circuit, another AND gating circuit having an output lead connected to said input terminal of said counting circuit, one input terminal connected to said complementary output terminals of said first concatenated flip-flop circuit, and another input lead connected to said inputting terminals.

Claim 9

Digital carrier wave detect circuitry as defined in claim 7 and wherein said other AND gating circuit has another input lead with an inverting circuit therein connected to an output terminal of said AND gating circuitry.

Claim 10

Digital carrier wave detect circuitry as defined in claim 7 and having at lease three concatenated edge triggered flip-flop circuits, and a plural input AND gating circuit having a plurality of input leads connected individually to the complementary output terminals of all of said concatenated flip-flop circuits save the last and having an output lead connected to said one input lead of said other AND gating circuit.

Claim 11

Digital carrier wave detect circuitry as defined in claim 5 and wherein said control circuitry further comprises an AND gating circuit having an output lead in said bidirectional counting circuit pulse input circuitry, one input lead coupled to said output terminal of said first of said concatenated flip-flop circuits and another input lead, a delay circuit connected between said other input lead and said inputting terminals.

Claim 12

Digital carrier wave detect circuitry as defined in claim 10 and wherein said control circuit further comprises an OR gating circuit interposed between said one input lead of said AND gating circuit and said first flip-flop circuit and having another input lead, and an AND gating circuit having an output lead connected to said other input lead of said OR gating circuit, one input lead connected to said complementary output terminal of said latching flip-flop circuit, and another input terminal coupled to a NAND gating circuit having input leads connected to the complementary output terminals of said first and last flip-flop circuits of said concatenated flip-flop circuits.

Claim 13

Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising input terminals at which a digital data modulated carrier wave signal is applied, output terminals at which a signal level indicative of carrier detected is presented, a delay circuit connected to said input terminals, an exclusive OR (XOR) gating circuit connected to said input terminals and to said delay circuit and having an output terminal at which transitions and noise pulses passing said input terminals and reappearing at the output of said XOR gating circuit appear, a latching flip-flop circuit having a set terminal connected to the output terminal of said XOR gating circuit, a reset terminal, and at least one output terminal, a number of concatenated flip-flop stages each having data, clock, and complementary output terminals, with the data terminal of the first stage connected to said one output terminal of said latching flip-flop circuit, with the erect output terminal of the first stage connected to the reset terminal of said latching flip-flop circuit, and with the erect terminal of each stage save the last stage connected to the data terminal of the succeeding stages, a set of complementary timing wave inputting terminals at which a source of complementary timing waves is applied with the terminals for the primary timing wave connected in common to the clock terminals of said concatenated flip-flop stages, a forward counter circuit having count input, reset and output terminals, four AND gating circuits having output terminals and having a multiple of input terminals permutated among said output terminals of said counter circuit for delivering output levels individual to said AND gating circuits and indicative of the maximum and minimum counts of two predetermined ranges of counts corresponding to said digital data conveyed by said signal, another latching flip-flop circuit having set, reset and complementary output terminals with one set of output terminals coupled to said carrier detect output terminals, an OR gating circuit connected to said set terminals of said latching flip-flop circuit and having input terminals individually connected to the output terminals of said AND gating circuits indicative of said predetermined minimum counts, another OR gating circuit connected to said reset terminals of said latching flip-flop circuit and having input terminals individually coupled to the output terminals of the other of said AND gating circuits, a counter input AND gating circuit having an output lead connected to the input terminals of said counter circuit and having at least three input leads with an inverting input circuit in one of said leads, a connection from the output terminal of the one AND gating circuit indicative of the greater of said maximum predetermined counts to said inverting input circuit, and another AND gating circuit having one input lead connected to the complementary timing wave inputting terminals for the secondary wave, another input connected to the output terminal of the last flip-flop stage of said concatenated flip-flop stages and an output lead connected to another input lead of said counter input AND gating circuit.

Claim 14

Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising input terminals at which a digital data modulated carrier wave signal is applied, output terminals at which a signal level indicative of carrier detected is presented, a delay circuit connected to said input terminals, an exclusive OR (XOR) gating circuit connected to said input terminals and to said delay circuit and having an output terminal at which transitions and noise pulses passing said input terminals and reappearing at the output of said XOR gating circuit appear, a latching flip-flop circuit having a set terminal connected to the output terminal of said XOR gating circuit, a reset terminal, and at least one output terminal, a number of concatenated flip-flop stages each having data, clock, and complementary output terminals, with the data terminal of the first stage connected to said one output terminal of said latching flip-flop circuit, with the erect output terminal of the first stage connected to the reset terminal of said latching flip-flop circuit, and with the erect terminal of each stage save the last stage connected to the data terminal of the succeeding stages, a set of complementary timing wave inputting terminals at which a source of complementary timing waves is applied with the terminals for the primary timing wave connected in common to the clock terminals of said concatenated flip-flop stages, a forward counter circuit having count input, reset and output terminals, four AND gating circuits having output terminals and having a multiple of input terminals permutated among said output terminals of said counter circuit for delivering output levels individual to said AND gating circuits and indicative of the maximum and minimum counts of two predetermined ranges of counts corresponding to said digital data conveyed by said signal, another latching flip-flop circuit having set, reset and complementary output terminals with one set of output terminals coupled to said carrier detect output terminals, an OR gating circuit connected to said set terminals of said latching flip-flop circuit and having input terminals individually connected to the output terminals of said AND gating circuits indicative of said predetermined minimum counts, another OR gating circuit connected to said reset terminals of said latching flip-flop circuit and having input terminals individually coupled to the output terminals of the other of said AND gating circuits, a counter input AND gating circuit having an output lead connected to the input terminals of said counter circuit and having at least three input leads with an inverting input circuit in one of said leads, a connection from the output terminal of the one AND gating circuit indicative of the greater of said maximum predetermined counts to said inverting input circuit, and another AND gating circuit having one input lead connected to the complementary timing wave inputting terminals for the secondary wave, another input connected to the output terminal of the last flip-flop stage of said concatenated flip-flop stages and an output lead connected to another input lead of said counter input AND gating circuit.

Claim 15

Digital carrier wave detect circuitry as defined in claim 12 and incorporating a further AND gating circuit having an output lead connected to another input lead of said counter input AND gating circuit and input leads connected to the complementary output terminals of all of said flip-flop stages save the last.

Claim 16

Digital carrier wave detect circuitry as defined in claim 12 and incorporating a bidirectional counter having one input terminal for counting in one direction, another input terminal for counting in the other direction, a count input terminal, output terminals connected to said signal level terminals, and terminals at which outputs signifying not all zeros and not all ones are presented, And gating circuitry connected to said one input terminal and having input leads connected to said terminals signifying not all ones and to the output terminals of said latching flip-flop circuit indicative of said properly spaced transitions, other AND gating circuitry connected to said other input terminal and having input leads connected to said terminals signifying not all zeros and to the other output terminals of said latching flip-flop circuit, and further AND gating circuitry having an output lead connected to said count pulse input terminal and having an input lead coupled to said primary timing wave input terminals, and other input lead coupled to said output terminal of said first flip-flop stage.

Claim 17

Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising input terminals at which at least the train of transitions of a digital data modulated carrier wave signal is applied, output terminals at which a signal level indicative of said carrier wave detected is presented, inputting terminals at which a clock pulse train is applied having a number of impulses greater than the number of said transitions of said wave for a given period of time, a counting circuit having reset, input and output terminals, comparing circuitry connected to said output terminals of said counting circuit and having output terminals at which electric levels are delivered for a plurality of predetermined counts corresponding to the appearance of said transitions in said modulated wave with respect to said impulses of said clock pulse train, control circuitry connected to said input terminals, to said inputting terminals and to said reset and input terminals of said counting circuit for gating said clock inpulses to said counting circuit for counting clock impulses between transitions of said modulated wave, and output circuitry coupled between said comparing circuitry output terminals and said signal level output terminals and responsive to a predetermined count for indicating properly spaced transitions.

Claim 18

Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising input terminals at which at least the train of transitions of a digital data modulated carrier wave signal is applied, output terminals at which a signal level indicative of said carrier wave detected is presented, inputting terminals at which a clock pulse train is applied having a number of impulses greater than the number of said transitions of said wave for a given period of time, a counting circuit having reset, input and output terminals, comparing circuitry connected to said output terminals of said counting circuit and having output terminals at which electric levels are delivered for a plurality of predetermined counts corresponding to the appearance of said transitions in said modulated wave with respect to said impulses of said clock pulse train, control circuitry connected to said input terminals, to said inputting terminals and to said reset and input terminals of said counting circuit for gating said clock inpulses to said counting circuit for counting clock impulses between transitions of said modulated wave, and output circuitry coupled between said comparing circuitry output terminals and said signal level output terminals and responsive to a predetermined count for indicating properly spaced transitions.