Abstract A clamped push-pull driver circuit suitable for driving high capacitive loads includes a bootstrap MOS inverter circuit driving an MOS push-pull driver circuit. A regulator circuit including a plurality of diode-connected MOSFETs is coupled between the output of the MOS bootstrap inverter and a ground conductor. A MOSFET (the feedback device) having its gate electrode coupled to the output of the MOS push-pull circuit is connected in series with the diode-connected MOSFETs. Rapid rise time and short delay are achieved at the output of the clamped push-pull driver circuit, since the regulator circuit does not begin to conduct current (i.e., does not start the clamping action) until the output voltage of the push-pull driver circuit has exceeded two thresholds. Thus a large drive capability is provided to initiate the rising action of the output signal and clamping only begins to occur after the output is already rising towards a higher virtual final level than that which clamping will allow. This delayed clamping action is controlled by the feedback MOSFET which is positioned between two of the diode-connected MOSFETs so that the feedback MOSFET is not turned on until the desired voltage is achieved at the output of the MOS push-pull driver circuit. The output of the MOS push-pull driver will continue to rise until it reaches a level which is one threshold below that set by the plurality of diode-connected MOSFETs. The final voltage, at the end of the rise time, at the output of the MOS push-pull driver circuit tracks with the MOS threshold voltage.
A circuit for producing a limited output voltage comprising: inverter means for producing a first voltage at a first node in response to an input voltage applied to said inverter means; output means coupled to said first node for producing a second voltage at a second node in response to said first voltage; and regulator means coupled to said first node and to said second node for limiting said first voltage in response to said second voltage, said regulator means including a plurality of insulated gate field effect transistors coupled in series between said first node and a first voltage conductor, one of said insulated gate field effect transistors having a gate electrode coupled to said second node, and the other of said insulated gate field effect transistors being diode-connected.
Claim 2
Dependent Claim
130 words
A circuit for producing a limited output voltage comprising: inverter means for producing a first voltage at a first node in response to an input voltage applied to said inverter means; output means coupled to said first node for producing a second voltage at a second node in response to said first voltage; and regulator means coupled to said first node and to said second node for limiting said first voltage in response to said second voltage, said regulator means including a plurality of insulated gate field effect transistors coupled in series between said first node and a first voltage conductor, one of said insulated gate field effect transistors having a gate electrode coupled to said second node, and the other of said insulated gate field effect transistors being diode-connected.
Claim 3
Dependent Claim
101 words
The circuit as recited in claim 1 wherein said inverter includes: a first insulated gate field effect transistor coupled between a second voltage conductor and said first node; a second insulated gate field effect transistor coupled between said second voltage conductor and a gate electrode of said first insulated gate field effect transistor; capacitor means coupled between a gate electrode and a source electrode of said first insulated gate field effect transistor; a third insulated gate field effect transistor coupled between said first node and said first voltage conductor and having its gate electrode coupled to said input of said inverter.
Claim 4
Dependent Claim
57 words
The circuit as recited in claim 1 wherein said output means includes a first insulated gate field effect transistor coupled between a second voltage conductor and said second node and having its gate electrode coupled to said first node, and a second insulated gate field effect transistor coupled between said second node and said first voltage conductor.