US3912948A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mos bootstrap inverter circuit
Assignee: Standard Microsystems LLC
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Filing: 1971-08-30
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Granted: 1975-10-14
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Expires: 1991-08-30
Abstract
Abstract An MOS bootstrap inverter circuit including at least four FET devices wherein one of the FET devices serves as an inverting amplifier, a second FET device serves as an active load for the inverting amplifier, a third FET device serves as a biasing means for the active load, and the gate-to-channel capacitance of a fourth FET device is used as a bootstrapping feedback element for the active load.
Inventors
- 👤 Dilip C Bapat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
211 words
An MOS bootstrap inverter circuit, comprising: an inverter output node; an inverting amplifier responsive to an input signal and operative to develop an inverted signal at said output node; an active load means including, a first silicon gate FET having a first gate, a first source coupled to said output node, and a first drain for connection to a first source of potential; biasing means coupling said first gate to said first drain; and means comprising a silicon gate FET forming a capacitor and including a first body of semiconductive material of a first conductivity type having a first surface, a second body of semiconductor material of a second conductivity type disposed within said first body and terminating in said first surface, an electrically conductive body disposed opposite a surface portion of said first body lying immediately adjacent to said second body, said conductive body forming a first plate of said capacitor, a dielectric layer disposed between said conductive body and said portion, means electrically coupling said conductive body to said first gate, and means electrically coupling said second body to said output node, whereby a predetermined difference in potential between said conductive body and said first body causes said portion to invert and form a sEcond plate of said capacitor.
Claim 2
Dependent Claim
211 words
An MOS bootstrap inverter circuit, comprising: an inverter output node; an inverting amplifier responsive to an input signal and operative to develop an inverted signal at said output node; an active load means including, a first silicon gate FET having a first gate, a first source coupled to said output node, and a first drain for connection to a first source of potential; biasing means coupling said first gate to said first drain; and means comprising a silicon gate FET forming a capacitor and including a first body of semiconductive material of a first conductivity type having a first surface, a second body of semiconductor material of a second conductivity type disposed within said first body and terminating in said first surface, an electrically conductive body disposed opposite a surface portion of said first body lying immediately adjacent to said second body, said conductive body forming a first plate of said capacitor, a dielectric layer disposed between said conductive body and said portion, means electrically coupling said conductive body to said first gate, and means electrically coupling said second body to said output node, whereby a predetermined difference in potential between said conductive body and said first body causes said portion to invert and form a sEcond plate of said capacitor.
Claim 3
Dependent Claim
20 words
An MOS bootstrap inverter circuit as recited in claim 1 wherein said conductive body includes a layer of polysilicon material.
Claim 4
Dependent Claim
112 words
In an MOS bootstrap inverter circuit including, an output node, an inverting amplifier responsive to an input signal and operative to develop an inverted signal at said output node, an active load means including a first silicon gate FET having a first gate and a first source coupled to said output node, and capacitive bootstrap circuit means for said active load means, an improved capacitive bootstrap circuit means, comprising: a second silicon gate FET having a second gate coupled to said first gate, a second source coupled to said output node, and a second drain, whereby the gate-to-channel capacitance of said second FET capacitively couples said first gate to said output node.
Claim 5
Dependent Claim
112 words
In an MOS bootstrap inverter circuit including, an output node, an inverting amplifier responsive to an input signal and operative to develop an inverted signal at said output node, an active load means including a first silicon gate FET having a first gate and a first source coupled to said output node, and capacitive bootstrap circuit means for said active load means, an improved capacitive bootstrap circuit means, comprising: a second silicon gate FET having a second gate coupled to said first gate, a second source coupled to said output node, and a second drain, whereby the gate-to-channel capacitance of said second FET capacitively couples said first gate to said output node.
Claim 6
Dependent Claim
24 words
In an MOS bootstrap inverter circuit as recited in claim 3 and further comprising means electrically shorting said second drain to said second source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-13 | 1979-04-14 | 1979-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-13 | 1983-04-14 | 1983-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-13 | 1987-04-14 | 1987-10-14 | $7700.00 | Window Closed / Lapsed |