Patent US4054804A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4054804A Expired / Lapsed US ⏱️ 0.0 years remaining

Bipolar charging and discharging circuit

Assignee: Nippon Tsushin Kogyo KK
•
Filing: 1976-10-01
•
Granted: 1977-10-18
•
Expires: 1996-10-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A timing circuit is disclosed in which the charging time constant in response to positive or negative pulses can be independently controlled. The discharging time constant in response to the removal of all signal pulses from the input of the circuit can be fixed differently from the charging time constants.

Inventors

  • 👤 Yuji Tanaka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 14:37
CPC Classifications
H; H03; H03K; H03K6/00

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 216 words
A timing circuit which has different charging time constants in response to positive and negative input signal pulses and a different discharging time constant in response to the removal of an input signal, said circuit comprising, a reference potential terminal, an input terminal for receiving said input positive and negative signal pulses, said pulses being of positive or negative potential with respect to the potential of said reference potential terminal, an output terminal, a capacitor connected between said output terminal and the reference potential terminal, a discharge resistor connected in parallel with said capacitor, a first series connection comprising a first charging resistor connected in series with a first switching means, said series connection being interposed between said input terminal and said output terminal, said first switching means being in a conducting state only when the input potential to said input terminal is at a level higher than said reference potential, and a second series connection comprising a second charging resistor connected in series with a second switching means, said series connection being interposed in parallel with said first series connection between the input terminal and the output terminal, said second switching means being in a conducting state only when the input potential to said input terminal is at a level lower than said reference potential.
Claim 2
Dependent Claim 216 words
A timing circuit which has different charging time constants in response to positive and negative input signal pulses and a different discharging time constant in response to the removal of an input signal, said circuit comprising, a reference potential terminal, an input terminal for receiving said input positive and negative signal pulses, said pulses being of positive or negative potential with respect to the potential of said reference potential terminal, an output terminal, a capacitor connected between said output terminal and the reference potential terminal, a discharge resistor connected in parallel with said capacitor, a first series connection comprising a first charging resistor connected in series with a first switching means, said series connection being interposed between said input terminal and said output terminal, said first switching means being in a conducting state only when the input potential to said input terminal is at a level higher than said reference potential, and a second series connection comprising a second charging resistor connected in series with a second switching means, said series connection being interposed in parallel with said first series connection between the input terminal and the output terminal, said second switching means being in a conducting state only when the input potential to said input terminal is at a level lower than said reference potential.
Claim 3
Dependent Claim 19 words
The charging and discharging circuit of claim 1 wherein said first and second switching devices are transistor switching circuits.
Claim 4
Dependent Claim 91 words
The charging and discharging circuit of claim 2 wherein, said first switching means is a PNP transistor the emitter of which is connected to said input terminal, the collector of which is connected to said first charging resistor, and the base of which is connected to said reference terminal, and said second switching means is an NPN transistor, the emitter of which is connected to said input terminal, the collector of which is connected to said second charging resistor, and the base of which is connected to said reference potential terminal.

References Cited (Backward Citations)

US3444393A Cited
US3497723A Cited
US3701909A Cited
US3838346A Cited
US4002927A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-10-17 1981-04-18 1981-10-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-10-17 1985-04-18 1985-10-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-10-17 1989-04-18 1989-10-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag