Bipolar sample and hold circuit with low-pass filtering

Claim 2

An analog sample and hold circuit comprising first and second operational amplifiers; network means for simultaneously applying an analog input signal to the two operational amplifiers; first and second feedback means for feeding back the output of the first and second operational amplifiers to their respective inputs; a capacitor for temporarily storing a sample of the input signal from the outputs of the first and second operational amplifiers; filtering network means, including the capacitor, for low-pass filtering the outputs of the operational amplifiers and coupling both filtered outputs to an output terminal; a first and a second means for coupling the filtered outputs at the output terminal to the first and second feedback means respectively; switching means for temporarily applying a hold pulse through the operational amplifiers to the filtering network means; said filtering means including means for blocking leakage from the capacitor to the operational amplifiers for the duration of the hold pulse.

Claim 3

A circuit as described in claim 1 wherein said filtering network means includes a high input impedance device connected between the capacitor and the output terminal.

Claim 4

A circuit as described in claim 2 wherein the high input impedance device is a unity gain amplifier and the capacitor is connected between the unity gain amplifier input and ground.

Claim 5

A circuit as described in claim 1 wherein each of said first and second feedback means includes two alternative paths between the output and input of its respective operational amplifier.

Claim 6

A circuit as described in claim 4 wherein the two alternative paths in each feedback means each include a diode, the diodes being connected with opposite polarities in each of the alternative paths of each feedback means.

Claim 7

A circuit as described in claim 1 wherein said means for blocking leakage is a pair of blocking diodes, each connected between the output of one of said operational amplifiers and the capacitor, said blocking diodes being connected in opposite polarity so that they conduct at mutually exclusive times, the amplitude of the hold pulse being greater than the amplitude of the input signal so that for the duration of a hold pulse both blocking diodes are rendered nonconductive, thereby preventing leakage of the capacitor into the operational amplifiers.

Claim 8

A circuit as described in claim 6 wherein a selected one diode in each feedback means is also rendered nonconducting by the hold pulse.

Claim 9

A circuit as described in claim 6 wherein each operational amplifier has a positive and a negative input terminal, one pair of like terminals being connected in common, said switching means including means for applying the hold pulse to the other terminal of the first operational amplifier directly and for applying an inverted hold pulse to the other terminal of the second operational amplifier.

Claim 10

An analog sample and hold circuit comprising: an input applied simultaneously to negative terminals of two operational amplifiers, the positive terminals of which are grounded; a capacitor; an output amplifier; the output of the output amplifier being coupled through a first resistor and a first diode connected in one polarity to the output of the first operational amplifier, the input of the output amplifier being connected directly to one side of the capacitor; said first operational amplifier output also being coupled in series to a second diode connected in one polarity, a second resistor and said one side of the capacitor, the other side of said capacitor being grounded; said output of the first operational amplifier also being coupled in series through a third resistor and a third diode of one polarity in series to the input of said first operational amplifier; a fourth resistor connected from the negative terminal of the operational amplifier to a node between said first diode and first resistor; the output of the output amplifier being coupled through a fifth resistor and fourth diode of the other polarity in series to the output of the second operational amplifier; said output of the second operational amplifier also being coupled in series to a fifth diode of the other polarity and a sixth resistor to said one side of said capacitor; said output of the second operational amplifier also being coupled in series through a seventh resistor and sixth diode of the other polarity to the input of said other operational amplifier; an eighth resistor connected from the input of the second operational amplifier to a node between fourth diode and the fifth resistor; a d.c. voltage source coupled through a switch to the negative terminal of the first operational amplifier, and coupled through the switch in series with an inverting amplifier to the negative terminal of the other operational amplifier.

Claim 11

An analog sample and hold circuit comprising: an input applied simultaneously to negative terminals of two operational amplifiers, the positive terminals of which are grounded; a capacitor; an output amplifier; the output of the output amplifier being coupled through a first resistor and a first diode connected in one polarity to the output of the first operational amplifier, the input of the output amplifier being connected directly to one side of the capacitor; said first operational amplifier output also being coupled in series to a second diode connected in one polarity, a second resistor and said one side of the capacitor, the other side of said capacitor being grounded; said output of the first operational amplifier also being coupled in series through a third resistor and a third diode of one polarity in series to the input of said first operational amplifier; a fourth resistor connected from the negative terminal of the operational amplifier to a node between said first diode and first resistor; the output of the output amplifier being coupled through a fifth resistor and fourth diode of the other polarity in series to the output of the second operational amplifier; said output of the second operational amplifier also being coupled in series to a fifth diode of the other polarity and a sixth resistor to said one side of said capacitor; said output of the second operational amplifier also being coupled in series through a seventh resistor and sixth diode of the other polarity to the input of said other operational amplifier; an eighth resistor connected from the input of the second operational amplifier to a node between fourth diode and the fifth resistor; a d.c. voltage source coupled through a switch to the negative terminal of the first operational amplifier, and coupled through the switch in series with an inverting amplifier to the negative terminal of the other operational amplifier.

Claim 12

An analog sample and hold circuit comprising a first operational amplifier; a capacitor; high input impedance means for isolating the capacitor; means for feeding back the output of said first operational amplifier via a first pair of two alternative paths to the input of said first operational amplifier; means for coupling the output of the high input impedance means to the output of the first operational amplifier; another operational amplifier; means for feeding back the output signal of said other operational amplifier via a second pair of two alternative paths to the input of said other operational amplifier; means for coupling the output of the high input impedance means to the output of the other operational amplifier; low-pass filtering means including the capacitor, for coupling the outputs of said first and said other operational amplifiers to the input of the high input impedance means; a network means for applying an analog input signal simultaneously to both operational amplifiers; switching means for temporarily applying a hold pulse through the operational amplifiers to the low-pass filtering network means to prevent leakage of the capacitor to the operational amplifiers for the duration of the hold pulse.

Claim 13

An analog sample and hold circuit comprising a first operational amplifier; a capacitor; high input impedance means for isolating the capacitor; means for feeding back the output of said first operational amplifier via a first pair of two alternative paths to the input of said first operational amplifier; means for coupling the output of the high input impedance means to the output of the first operational amplifier; another operational amplifier; means for feeding back the output signal of said other operational amplifier via a second pair of two alternative paths to the input of said other operational amplifier; means for coupling the output of the high input impedance means to the output of the other operational amplifier; low-pass filtering means including the capacitor, for coupling the outputs of said first and said other operational amplifiers to the input of the high input impedance means; a network means for applying an analog input signal simultaneously to both operational amplifiers; switching means for temporarily applying a hold pulse through the operational amplifiers to the low-pass filtering network means to prevent leakage of the capacitor to the operational amplifiers for the duration of the hold pulse.