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US4054788A
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Modular binary half-adder
Assignee: HP Inc
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Filing: 1976-06-04
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Granted: 1977-10-18
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Expires: 1996-06-04
Abstract
Abstract Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits, thus allowing rapid propagation of such carry bits to more significant digits and subsequent parallel summation of the sum bits using the carry bits previously calculated.
Inventors
- 👤 David Steven Maitland
- 👤 Sandy Lee Chumbley
- 👤 Havyn E. Bradley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:38
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
290 words
Binary half-adder module comprising: a storage element for retaining a logical bit of binary data in states corresponding to either a logical "1" or a logical "0", wherein the output can be monitored while the input is being changed; a first inverter responsive to the output of said storage element for providing a logical signal complementary to the logical output of said storage element; means for applying an input carry signal (corresponding to either a logical "1" or a logical "0") to said binary half-adder module; a second inverter responsive to said input carry signal for providing a logical signal complementary to said input carry signal; means for charging an output carry line; means for applying an increment signal to said binary half-adder module; means for discharging said output carry line upon detection of a charge on the logical output of said storage element and detection of said increment signal; means for discharging said output carry line upon detection of said input carry signal corresponding to a logical "0" ; means for applying a decrement signal to the binary half-adder module; means for discharging said output carry line upon detection of a signal corresponding to a logical "1" on the output of said first inverter and detection of said decrement signal; means for applying an update signal to an update signal line; means for recirculating the contents of said storage element upon detection of signals corresponding to the logical "1" on the output of said second inverter and the update signal line; and means for loading the signal on the output of said first inverter into the storage element upon detection of said input carry signal and said signal on the update signal line each corresponding to a logical "1"
Claim 2
Dependent Claim
290 words
Binary half-adder module comprising: a storage element for retaining a logical bit of binary data in states corresponding to either a logical "1" or a logical "0", wherein the output can be monitored while the input is being changed; a first inverter responsive to the output of said storage element for providing a logical signal complementary to the logical output of said storage element; means for applying an input carry signal (corresponding to either a logical "1" or a logical "0") to said binary half-adder module; a second inverter responsive to said input carry signal for providing a logical signal complementary to said input carry signal; means for charging an output carry line; means for applying an increment signal to said binary half-adder module; means for discharging said output carry line upon detection of a charge on the logical output of said storage element and detection of said increment signal; means for discharging said output carry line upon detection of said input carry signal corresponding to a logical "0" ; means for applying a decrement signal to the binary half-adder module; means for discharging said output carry line upon detection of a signal corresponding to a logical "1" on the output of said first inverter and detection of said decrement signal; means for applying an update signal to an update signal line; means for recirculating the contents of said storage element upon detection of signals corresponding to the logical "1" on the output of said second inverter and the update signal line; and means for loading the signal on the output of said first inverter into the storage element upon detection of said input carry signal and said signal on the update signal line each corresponding to a logical "1"
Claim 3
Dependent Claim
35 words
A binary counter comprising a plurality of binary half-adder modules as in claim 1 wherein the output carry line of one module comprises the means for applying an input carry signal to a second module.
Claim 4
Dependent Claim
32 words
A binary counter as in claim 2 wherein the update signal lines of said binary half-adder modules are a line common to all other binary half-adder modules included in said binary counter.
Claim 5
Dependent Claim
249 words
A binary logic module adapted to receive a first input signal I, a second input signal I complementary to the first input signal, and a carry-in signal C, said module for providing a carry-out signal K and an output signal S, each signal having a voltage level corresponding to either a logical "1" or a logical "0", the module comprising: first MOS inverter logic means responsive to the carry-in signal C for providing a first control signal in response to the carry-in signal C corresponding to a logical "0" and for providing a second control signal in response to the carry-in signal C corresponding to a logical "1"; means for presetting the carry-out signal K to a first predetermined voltage level corresponding to a logical "1"; Mos carry logic means coupled to receive the first control signal and the second input signal I for setting the carry-out signal K to a second predetermined voltage level corresponding to logical "0" in response to either receiving a first control signal or in response to receiving a second input signal I corresponding to a logical "1"; and Mos output logic means coupled to receive the first and second control signals, the first input signal I, and the second input signal I, for providing an output signal S corresponding to the input signal I in response to receiving the first control signal and for providing an output signal S corresponding to the complementary signal I in response to receiving the second control signal.
Claim 6
Dependent Claim
249 words
A binary logic module adapted to receive a first input signal I, a second input signal I complementary to the first input signal, and a carry-in signal C, said module for providing a carry-out signal K and an output signal S, each signal having a voltage level corresponding to either a logical "1" or a logical "0", the module comprising: first MOS inverter logic means responsive to the carry-in signal C for providing a first control signal in response to the carry-in signal C corresponding to a logical "0" and for providing a second control signal in response to the carry-in signal C corresponding to a logical "1"; means for presetting the carry-out signal K to a first predetermined voltage level corresponding to a logical "1"; Mos carry logic means coupled to receive the first control signal and the second input signal I for setting the carry-out signal K to a second predetermined voltage level corresponding to logical "0" in response to either receiving a first control signal or in response to receiving a second input signal I corresponding to a logical "1"; and Mos output logic means coupled to receive the first and second control signals, the first input signal I, and the second input signal I, for providing an output signal S corresponding to the input signal I in response to receiving the first control signal and for providing an output signal S corresponding to the complementary signal I in response to receiving the second control signal.
Claim 7
Dependent Claim
115 words
A binary logic module as in claim 4 further adapted to receive an increment signal P and a decrement signal M, wherein said MOS carry logic means is further coupled to receive the first input signal I, and further comprises means for selectively receiving the first input signal I only in response to receiving a decrement signal M, and for selectively receiving the second input signal I only in response to receiving an increment signal P, said MOS carry logic means further comprising means for setting the carry-out signal K to the second predetermined voltage level corresponding to a logical "0" in response to receiving a first input signal I corresponding to a logical "1".
Claim 8
Dependent Claim
151 words
A binary half-adder module comprising a binary logic module as in claim 4 and further comprising: a delay element for retaining a logical bit of binary data in states corresponding to either a logical "1" or a logical "0", said delay element having an input and an output wherein said delay element applies a signal to the output thereof corresponding to a signal previously applied to the input thereof, the input thereof coupled to said MOS output logic means to receive the sum signal S; and a first inverter responsive to the signal on the output of said delay element, said inverter for providing a logical signal complementary to the signal upon the output of said delay element, the signal on the output of said delay element and the logical signal provided by said first inverter providing the first and second input signals I and I to said binary logic module.
Claim 9
Dependent Claim
35 words
A binary counter comprising a plurality of binary half-adder modules as in claim 6 wherein the output carry line of one module comprises the means for applying an input carry signal to a second module.
Claim 10
Dependent Claim
32 words
A binary counter as in claim 7 wherein the update signal line of said binary half-adder modules is a line common to all other binary half-adder modules included in said binary counter.
Claim 11
Dependent Claim
31 words
A binary half-adder module as in claim 6 wherein said first MOS inverter logic means and said MOS carry logic means each comprise a resistive element in series with a MOSFET.
Claim 12
Dependent Claim
54 words
A binary half-adder module as in claim 9 wherein said MOS carry logic means comprises two MOSFETS with gates coupled to the first control signal and second input signal I, respectively, drains coupled to signal line means for propagating the carry-out signal K, and sources coupled to a source of the second predetermined level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |