Patent US4050965A successfully refreshed from Google Patents.
US4050965A
Expired / Lapsed
US
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Simultaneous fabrication of CMOS transistors and bipolar devices
Assignee: United States Department of the Air Force
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Filing: 1975-10-21
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Granted: 1977-09-27
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Expires: 1995-10-21
Abstract
Abstract A process for the simultaneous fabrication of CMOS transistors and bipolar devices on the same integrated circuit. The process follows the standard Silicon-Gate Deep Depletion technology up through gate definition. An additional mask step is included for definition of the base implant region. After the base diffusion the process again follows the standard approach resulting in a new structure which permits the fabrication of CMOS/SOS as well as a bipolar driver transistor.
Inventors
- 👤 Alfred C. Ipri
- 👤 John C. Sarace
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:51
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/03
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
152 words
A process for the fabrication of a bipolar device being comprised of forming a dielectric substrate of sapphire, depositing an epitaxial layer of semiconducting material thereupon in a single crystal fashion, forming semiconductor islands by an etching technique leaving regions of material where the bipolar device is to be formed, oxidizing the formed semiconductor islands, depositing poly-crystalline silicon thereupon, defining the deposited poly-crystalline silicon, base doping the bipolar device on one side of the device, diffusing the base doping, N+ doping for the emitter of the bipolar device with the edge of the formed poly-silicon gate being the diffusion edge for both the base and emitter diffusion, the N+ doping also making better contact to the collector region, as well as for source-drain n-channel device doping, P+ doping for "p" channel source drain, base contacting, driving in diffusion sources N+ and P+, opening contacts, and forming metal interconnects to complete the circuit.
Claim 2
Dependent Claim
152 words
A process for the fabrication of a bipolar device being comprised of forming a dielectric substrate of sapphire, depositing an epitaxial layer of semiconducting material thereupon in a single crystal fashion, forming semiconductor islands by an etching technique leaving regions of material where the bipolar device is to be formed, oxidizing the formed semiconductor islands, depositing poly-crystalline silicon thereupon, defining the deposited poly-crystalline silicon, base doping the bipolar device on one side of the device, diffusing the base doping, N+ doping for the emitter of the bipolar device with the edge of the formed poly-silicon gate being the diffusion edge for both the base and emitter diffusion, the N+ doping also making better contact to the collector region, as well as for source-drain n-channel device doping, P+ doping for "p" channel source drain, base contacting, driving in diffusion sources N+ and P+, opening contacts, and forming metal interconnects to complete the circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-26 | 1981-03-28 | 1981-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-26 | 1985-03-28 | 1985-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-26 | 1989-03-28 | 1989-09-27 | $7700.00 | Window Closed / Lapsed |