Process for fabricating non-volatile field effect semiconductor memory structure utilizing implanted ions to induce trapping states

Claim 2

A process for fabricating a non-volatile field effect memory cell comprising the steps of: a. forming active field effect transistor regions, including a source region, a gate region, and a drain region, on a silicon semi-insulating substrate; b. forming a first layer of silicon dioxide on top of said gate region; c. implanting ions into said silicon dioxide layer near the silicon interface whereby said implanted ions provide charge trapping sites for non-volatile memory operation; d. annealing said structure in a nonoxidizing ambient at a predetermined elevated temperature sufficient to diffuse any of said ions that have reached into said substrate but not affecting significantly the distribution of ions implanted into said fist silicon dioxide layer; e. thermally growing a second layer of silicon dioxide under said first layer of silicon dioxide.

Claim 3

A process as set forth in claim 1 wherein: a. said implanted ions belong to a species selected from a group consisting of aluminum, tungsten, titanium, gold, molybdenum and chromium; b. said second layer of silicon dioxide is formed to a thickness ranging between 5 and 100 angstroms.

Claim 4

A process for fabricating a non-volatile field effect memory device comprising the steps of: a. forming a source region, a gate region and a drain region on a surface of a semi-insulating silicon substrate; b. forming a first layer of silicon dioxide on top of said surface; c. implanting ions belonging to a species selected from a group consisting of aluminum, tungsten, titanium, gold, molybdenum and chromium into a section of said first silicon dioxide layer lying over the gate region at controlled depths and dosages whereby the distribution of said ions peaks close to the silicon and silicon dioxide interface; d. annealing said structure at a predetermined elevated temperature sufficient to disperse through diffusion any ions that may have reached said substrate while not significantly affecting the distribution of said ions implanted into said silicon dioxide whereby obtaining a structure where said implanted ions are concentrated in said gate silicon dioxide in close proximity to said silicon interface; e. forming through thermal oxidation a second and relatively thin layer of silicon dioxide under said first layer of silicon dioxide; f. forming ohmic contact means on said source region, on said drain region and on said implanted silicon dioxide layer on top of said gate region.

Claim 5

A process for fabricating a non-volatile field effect memory device comprising the steps of: a. forming a source region, a gate region and a drain region on a surface of a semi-insulating silicon substrate; b. forming a first layer of silicon dioxide on top of said surface; c. implanting ions belonging to a species selected from a group consisting of aluminum, tungsten, titanium, gold, molybdenum and chromium into a section of said first silicon dioxide layer lying over the gate region at controlled depths and dosages whereby the distribution of said ions peaks close to the silicon and silicon dioxide interface; d. annealing said structure at a predetermined elevated temperature sufficient to disperse through diffusion any ions that may have reached said substrate while not significantly affecting the distribution of said ions implanted into said silicon dioxide whereby obtaining a structure where said implanted ions are concentrated in said gate silicon dioxide in close proximity to said silicon interface; e. forming through thermal oxidation a second and relatively thin layer of silicon dioxide under said first layer of silicon dioxide; f. forming ohmic contact means on said source region, on said drain region and on said implanted silicon dioxide layer on top of said gate region.

Claim 6

In an improved process of fabricating a field effect memory cell comprising the steps of forming source, gate and drain regions on a semi-insulating silicon substrate and forming a first layer of silicon dioxide for a gate insulation the improvement which comprises the steps of: a. implanting a predetermined type of ions into a section of said first silicon dioxide layer near the silicon interface whereby said implanted ions provide charge trapping sites for non-volatile memory operation; b. annealing said substrate in a nonoxidizing ambient at a predetermined elevated temperature to thin out through diffusion any of said implanted ions that reached into said substrate; c. thermally growing a second layer of silicon dioxide under the first silicon dioxide layer whereby said trapping sites are separated from said substrate by a relatively pure layer of silicon dioxide having a predetermined thickness.

Claim 7

In an improved process of fabricating a field effect memory cell comprising the steps of forming source, gate and drain regions on a semi-insulating silicon substrate and forming a first layer of silicon dioxide for a gate insulation the improvement which comprises the steps of: a. implanting a predetermined type of ions into a section of said first silicon dioxide layer near the silicon interface whereby said implanted ions provide charge trapping sites for non-volatile memory operation; b. annealing said substrate in a nonoxidizing ambient at a predetermined elevated temperature to thin out through diffusion any of said implanted ions that reached into said substrate; c. thermally growing a second layer of silicon dioxide under the first silicon dioxide layer whereby said trapping sites are separated from said substrate by a relatively pure layer of silicon dioxide having a predetermined thickness.

Claim 8

A process as set forth in claim 4 wherein: a. said implanted ions belong to a species selected from a group consisting of aluminum, tungsten, titanium, gold, molybdenum and chromium; and b. said second layer of silicon dioxide is formed to a thickness ranging between 5 and 100 angstroms.