Patent US4040015A successfully refreshed from Google Patents.
US4040015A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary mos logic circuit
Assignee: Hitachi Ltd
•
Filing: 1976-06-22
•
Granted: 1977-08-02
•
Expires: 1996-06-22
Abstract
Abstract A dynamic complementary metal -oxide-semiconductor circuit (CMOS) includes a pair of gate stages connected in cascade. The first gate stage includes a first logic block which effects a prescribed logical function, the logic block being connected between a P-type and the N-type MOSFET. The source electrodes of the P-type and the N-type MOSFETs are connected between a power supply and ground, respectively, and their gate electrodes are connected in common. Moreover, the first gate stage has its output terminal connected to a load capacitor. The second logic block is also connected between a P-type MOSFET and an N-type MOSFET. The source electrodes of these MOSFETs are connected between a power supply and ground, respectively, while the gate electrodes thereof are connected in common. Also, a second load capacitor is connected to the output of the second gate stage. A pair of pulse signals, inverted with respect to each other, are applied to the first and second gate stages for driving the same, respectively. One of the MOSFETs making up the second logic block is of the type and is connected so that, when the power supply voltage applied to the gate thereof from the first gate stage, that MOSFET is turned "off". As a result, the possibility of misoperation due to the decrease in the charge of the first load capacitor, at the output of the first gate stage, is prevented.
Inventors
- 👤 Hideki Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:17
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; G; G11; G11C; G11C17/00; G11C17/04; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
759 words
A read-only memory comprising a first gate stage matrix formed of m columns of first gate stages and n rows of logic input lines, each first gate stage having a pair of clock controlled driving MOS transistors connected in series with a first logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said first logic block connected to a respective one of said logic input lines, between first and second sources of reference potential, said first logic block having a logic output terminal connected to one of the MOS transistors therein, a second gate stage matrix formed of p columns of second gate stages and m rows of logic input lines, each second gate stage having a pair of clock controlled driving MOS transistors connected in series with a second logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said second logic block connected to a respective one of the logic input lines of said m rows of logic input lines, between said second and first sources of reference potential, said second logic block having a logic output terminal connected to one of the MOS transistors therein, the gate electrode of an MOS transistor of said second logic block being connected to the logic output terminal of a respective first logic block in said first gate stage matrix. a third gate stage matrix formed of q columns of third gate stages and p rows of logic input lines, each third gate stage having a pair of clock controlled driving MOS transistors connected in series with a third logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said third logic block connected to a respective one of the logic input lines of said p rows of logic input lines, between said first and second sources of reference potential, said third logic block having a logic output terminal connected to one of the MOS transistors therein, the gate electrode of an MOS transistor of said third logic block being connected to the logic output terminal of a respective second logic block in said second gate stage matrix, a first clock line, connected to the clock controlled driving transistors in said first and third gate stage matrices, for supplying a first clock signal thereto, and a second clock line, connected to the clock controlled driving transistors in said second gate stage matrix, for supplying a second clock signal, which is the inverse of said first clock signal, thereto, and wherein the conductivity type of the at least one MOS transistor making up said second logic block is opposite the conductivity type of the at least one MOS transistor making up said first and third logic blocks, the driving MOS transistors and the first logic blocks in each first gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during first repeated intervals of said first clock signal for rendering the output potential of said first gate stage equal to said first reference potential irrespective of the state of said first logic block and the other of the driving MOS transistors therein conductive during second repeated intervals, alternating with said first repeating intervals of said first clock signal, for enabling the output potential of each first gate stage to change to a potential equal to the second reference potential depending on the state of said first logic block, the driving MOS transistors and the second logic block in each second gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during said first repeated intervals for rendering the output potential of each second gate stage equal to said second reference potential, the output potential of each second gate stage being enabled to change to a potential equal to said first reference potential depending on the state of the second logic block thereof, and the driving MOS transistors and the third logic block in each third gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during said first repeated intervals for rendering the output potential of each third gate stage equal to said first reference potential, the output potential of each third gate stage being enabled to change to a potential equal to said second reference potential depending on the state of said third logic block.
Claim 2
Dependent Claim
759 words
A read-only memory comprising a first gate stage matrix formed of m columns of first gate stages and n rows of logic input lines, each first gate stage having a pair of clock controlled driving MOS transistors connected in series with a first logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said first logic block connected to a respective one of said logic input lines, between first and second sources of reference potential, said first logic block having a logic output terminal connected to one of the MOS transistors therein, a second gate stage matrix formed of p columns of second gate stages and m rows of logic input lines, each second gate stage having a pair of clock controlled driving MOS transistors connected in series with a second logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said second logic block connected to a respective one of the logic input lines of said m rows of logic input lines, between said second and first sources of reference potential, said second logic block having a logic output terminal connected to one of the MOS transistors therein, the gate electrode of an MOS transistor of said second logic block being connected to the logic output terminal of a respective first logic block in said first gate stage matrix. a third gate stage matrix formed of q columns of third gate stages and p rows of logic input lines, each third gate stage having a pair of clock controlled driving MOS transistors connected in series with a third logic block made up of at least one MOS transistor which has its gate electrode corresponding to a logic input terminal for said third logic block connected to a respective one of the logic input lines of said p rows of logic input lines, between said first and second sources of reference potential, said third logic block having a logic output terminal connected to one of the MOS transistors therein, the gate electrode of an MOS transistor of said third logic block being connected to the logic output terminal of a respective second logic block in said second gate stage matrix, a first clock line, connected to the clock controlled driving transistors in said first and third gate stage matrices, for supplying a first clock signal thereto, and a second clock line, connected to the clock controlled driving transistors in said second gate stage matrix, for supplying a second clock signal, which is the inverse of said first clock signal, thereto, and wherein the conductivity type of the at least one MOS transistor making up said second logic block is opposite the conductivity type of the at least one MOS transistor making up said first and third logic blocks, the driving MOS transistors and the first logic blocks in each first gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during first repeated intervals of said first clock signal for rendering the output potential of said first gate stage equal to said first reference potential irrespective of the state of said first logic block and the other of the driving MOS transistors therein conductive during second repeated intervals, alternating with said first repeating intervals of said first clock signal, for enabling the output potential of each first gate stage to change to a potential equal to the second reference potential depending on the state of said first logic block, the driving MOS transistors and the second logic block in each second gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during said first repeated intervals for rendering the output potential of each second gate stage equal to said second reference potential, the output potential of each second gate stage being enabled to change to a potential equal to said first reference potential depending on the state of the second logic block thereof, and the driving MOS transistors and the third logic block in each third gate stage are arranged so that one of the driving MOS transistors therein is rendered conductive during said first repeated intervals for rendering the output potential of each third gate stage equal to said first reference potential, the output potential of each third gate stage being enabled to change to a potential equal to said second reference potential depending on the state of said third logic block.
Claim 3
Dependent Claim
21 words
The MOS logic circuit according to claim 1, wherein the driving MOS transistors of each respective stage have opposite conductivity types.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-01 | 1981-01-31 | 1981-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-01 | 1985-01-31 | 1985-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-01 | 1989-01-31 | 1989-08-02 | $7700.00 | Window Closed / Lapsed |