Clamping circuit

Claim 1

An integrated circuit for preventing transient substrate current injection comprising: (a) a semiconductor substrate of P conductivity type, (b) a layer of N conductivity type disposed over said substrate, (c) isolating means disposed into said layer for forming a plurality of isolated regions, (d) first means for coupling a voltage supply of a given magnitude and polarity to said semiconductor substrate, (e) second means coupled to at least one of said plurality of isolated regions for coupling an electrical signal thereto, said electrical signal having a magnitude and polarity capable of forward biasing the PN junction formed between said semiconductor substrate and a portion of said at least one of said plurality of isolated regions, (f) clamping circuit means to coupled to said at least one of said plurality of isolated regions for preventing said PN junction from becoming forward biased as a result of said electrical signal, said clamping circuit means including a clamping transistor for providing a high impedance state and a low impedance state in accordance with the amount of its emitter current, semiconductor junction means having first and second terminals, a first node coupled to said first terminal and to the base terminal of said clamping transistor, said second terminal being coupled to said voltage supply, regenerative semiconductor feedback circuit means coupled between said clamping transistor collector terminal and the first node for increasing current flow at the first node in response to the clamping transistor being driven to a lower impedance state in response to said electrical signal being coupled to the emitter terminal of said clamping transistor.