US3704383A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor-transistor logic clipping circuit
Assignee: AT&T Inc
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Filing: 1971-12-03
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Granted: 1972-11-28
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Expires: 1991-12-03
Abstract
Abstract The invention is a combination of a transistor-transistor logic (TTL) gate and a multi-emitter transistor clipping circuit having a different emitter connected to each input of the gate. The multi-emitter transistor is biased so that any signal, reflected by an input of the gate and tending to pull the potential of that input below ground, causes the transistor to conduct and clip the input signal essentially at ground potential.
Inventors
- 👤 Cyrus Frank Ault
- 👤 Ray Allen Reed
- 👤 William George Reichert Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
91 words
A circuit comprising a TTL gate having plural input terminals, each terminal being adapted for receiving a signal of either a first or a second potential, means for clipping the signals applied to the input terminals substantially at the first potential, the clipping means including a common-base connected multi-emitter transistor, means for connecting a different emitter electrode of the transistor to each input terminal of the gate, and means for biasing a base electrode of the transistor at a potential offset by one forward-biased p-n junction drop from the first potential.
Claim 2
Dependent Claim
91 words
A circuit comprising a TTL gate having plural input terminals, each terminal being adapted for receiving a signal of either a first or a second potential, means for clipping the signals applied to the input terminals substantially at the first potential, the clipping means including a common-base connected multi-emitter transistor, means for connecting a different emitter electrode of the transistor to each input terminal of the gate, and means for biasing a base electrode of the transistor at a potential offset by one forward-biased p-n junction drop from the first potential.
Claim 3
Dependent Claim
69 words
A circuit in accordance with claim 1 further comprising a source of fixed potential applied to a collector electrode of the transistor, the biasing means including a resistor and a diode connected in series circuit between the fixed potential source and the first potential, the diode being forward-biased during quiescent operation, and means connecting a junction between the resistor and the diode to the base electrode of the transistor.
Claim 4
Dependent Claim
25 words
A circuit in accordance with claim 2 wherein operating characteristics of the diode are closely matched with operating characteristics of base-emitter junctions of the transistor.
Claim 5
Dependent Claim
39 words
A circuit in accordance with claim 3 wherein the diode is fabricated as a transistor with base and collector electrodes short-circuited by a conductor and wherein the diode and the transistor are constructed as one planar silicon integrated circuit.
Claim 6
Dependent Claim
96 words
A planar integrated semiconductor circuit comprising a TTL gate having plural input terminals, means for clipping signals applied to the input terminals, the clipping means including a multi-emitter transistor having a different emitter electrode connected to each input terminal of the gate, and means for biasing the multi-emitter transistor so that it conducts an emitter current IIN substantially equal to IC2 epsilon IN , wherein IC2 is a reference current, epsilon is the base of natural logarithms, theta is a temperature dependent factor, and VIN is an input signal voltage on one of the input terminals.
Claim 7
Dependent Claim
96 words
A planar integrated semiconductor circuit comprising a TTL gate having plural input terminals, means for clipping signals applied to the input terminals, the clipping means including a multi-emitter transistor having a different emitter electrode connected to each input terminal of the gate, and means for biasing the multi-emitter transistor so that it conducts an emitter current IIN substantially equal to IC2 epsilon IN , wherein IC2 is a reference current, epsilon is the base of natural logarithms, theta is a temperature dependent factor, and VIN is an input signal voltage on one of the input terminals.
Claim 8
Dependent Claim
63 words
A cIrcuit in accordance with claim 5 wherein the biasing means comprise a diode conducting the current IC2, said diode is referenced at one of its terminals by a voltage that is substantially equal to one level of two input signal levels applied alternatively to the terminals, said diode is connected directly from its other terminal to a base electrode of the transistor.
Claim 9
Dependent Claim
39 words
A circuit in accordance with claim 6 wherein the biasing means further comprise a source of reference potential connected to a collector electrode of the transistor, and a resistor coupling the source to the base electrode of the transistor.
References Cited (Backward Citations)
US3518449A
Cited
US3553486A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-28 | 1976-05-29 | 1976-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-28 | 1980-05-29 | 1980-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-28 | 1984-05-29 | 1984-11-28 | $7700.00 | Window Closed / Lapsed |