US3681623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Geometric current amplifier
Assignee: International Business Machines Corp
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Filing: 1970-12-31
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Granted: 1972-08-01
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Expires: 1990-12-31
Abstract
Abstract A three terminal circuit comprised of two semiconductor transistors of opposite polarity types and two semiconductor diodes. These semiconductors are interconnected so as to provide positive regenerative feedback in a manner which permits achieving highly stable, temperature insensitive circuit characteristics which can be made independent of circuit parameters. The circuit requires no resistors, capacitors or inductors and may be used with particular advantage in integrated circuit form. Use of the circuit as an impedance converter, current generator, voltage regulator and differential amplifier are illustrated.
Inventors
- 👤 Harry S Hoffman Jr
- 👤 Jerry Saia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:33
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/22; G05F3/222; G05F3/225; H; H03; H03F; H03F1/00; H03F1/30; H03F1/302; H03F1/32; H03F3/00; H03F3/189; H03F3/19; H03F3/195; H03F3/34; H03F3/343; H03F3/347; H03H; H03H11/00; H03H11/02; H03H11/40
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
305 words
A linear current translating circuit comprising a three terminal network comprising first and second terminals defining a first current path, and a third terminal defining with said first terminal a second current path, a first semiconductor junction transistor in said first path having its emitter connected directly to said first terminal, a first semiconductor junction diode in said second path having one pole connected directly to said first terminal and being poled in the same sense as the emitter base junction of said first transistor, a first direct cross connection from the second pole of said first diode to the base of said first transistor, a second semiconductor junction transistor, of the opposite conductivity type than said first transistor, connected in said second path with its collector connected directly to said second pole of said first diode and its emitter connected directly to said third terminal, and having its base connected directly to the collector of said first transistor, whereby a first approximation relationship of currents in said paths is dictated by the ratio of the effective junction areas and resulting potential drops in said first diode and said first transistor emitter base junction, and a second semiconductor junction diode poled in the same sense as said emitter base junction of said second transistor and connected in said first path directly between the collector of said first transistor and said second terminal, the ratio of the area of the emitter base junction of said second transistor to the area of the diode junction of said second diode being essentially the same as the corresponding area ratio of said first diode to said first transistor, whereby the second diode and second transistor operate to maintain said second and third terminals at essentially the same potential over a wide operating range of currents in the two paths.
Claim 2
Dependent Claim
305 words
A linear current translating circuit comprising a three terminal network comprising first and second terminals defining a first current path, and a third terminal defining with said first terminal a second current path, a first semiconductor junction transistor in said first path having its emitter connected directly to said first terminal, a first semiconductor junction diode in said second path having one pole connected directly to said first terminal and being poled in the same sense as the emitter base junction of said first transistor, a first direct cross connection from the second pole of said first diode to the base of said first transistor, a second semiconductor junction transistor, of the opposite conductivity type than said first transistor, connected in said second path with its collector connected directly to said second pole of said first diode and its emitter connected directly to said third terminal, and having its base connected directly to the collector of said first transistor, whereby a first approximation relationship of currents in said paths is dictated by the ratio of the effective junction areas and resulting potential drops in said first diode and said first transistor emitter base junction, and a second semiconductor junction diode poled in the same sense as said emitter base junction of said second transistor and connected in said first path directly between the collector of said first transistor and said second terminal, the ratio of the area of the emitter base junction of said second transistor to the area of the diode junction of said second diode being essentially the same as the corresponding area ratio of said first diode to said first transistor, whereby the second diode and second transistor operate to maintain said second and third terminals at essentially the same potential over a wide operating range of currents in the two paths.
Claim 3
Dependent Claim
40 words
The invention in accordance with claim 1, wherein said circuit includes only semiconductors and all significant potential differences are provided by semiconductor junction drops, and said circuit is provided in integrated circuit form for uniformity of materials and ambient parameters.
Claim 4
Dependent Claim
88 words
The invention in accordance with claim 1, wherein the interconnecting means is arranged so that the relationship between the current Io flowing in said third terminal and the current Ir flowing in said second terminal is Io Ir/K, K being defined by the equation where AT1 and AD1 are respective effective junction areas of said first transistor and said first diode, a1 and a2 are the respective alphas of said first and second transistors, and b1 and b2 are the respective betas of said first and second transistors.
Claim 5
Dependent Claim
25 words
The invention in accordance with claim 3, wherein said alphas and betas are chosen so that K may be approximated by the equation K AT1/AD1
Claim 6
Dependent Claim
56 words
The combination of claim 1 with circuit means attached to the first, second and third terminals establishing a current in said first terminal which will operate the semiconductor devices at levels above cut off and below saturation and which permit the potentials at said second and third terminals to establish themselves at substantially the same level.
Claim 7
Dependent Claim
189 words
In combination, first and second semiconductor transistors of opposite polarity types, first and second semiconductor diodes, and interconnecting means coupled to said transistors and said diodes for forming a three terminal circuit providing positive regenerative feedback with respect to a change in a current flowing in a terminal of said three terminal circuit, wherein said circuit includes only semiconductors and no resistors, capacitors or inductors, wherein said transistors ad diodes are of the junction type, and wherein said interconnecting means is arrange so that the relationship between the current Io flowing in said terminal and the current Ir flowing in a second terminal is Io Ir/K K being defined by the equation where AT1 and AD1 are respective effective junction areas of said first transistor and said first diode, a1 and a2 are the respective alphas of said first and second transistors, and b1 and b2 are the respective betas of said first and second transistors, wherein two of said circuits are connected in cascade by connection of the output terminal of the first circuit and input terminal of the second circuit to a common external constant current circuit.
Claim 8
Dependent Claim
189 words
In combination, first and second semiconductor transistors of opposite polarity types, first and second semiconductor diodes, and interconnecting means coupled to said transistors and said diodes for forming a three terminal circuit providing positive regenerative feedback with respect to a change in a current flowing in a terminal of said three terminal circuit, wherein said circuit includes only semiconductors and no resistors, capacitors or inductors, wherein said transistors ad diodes are of the junction type, and wherein said interconnecting means is arrange so that the relationship between the current Io flowing in said terminal and the current Ir flowing in a second terminal is Io Ir/K K being defined by the equation where AT1 and AD1 are respective effective junction areas of said first transistor and said first diode, a1 and a2 are the respective alphas of said first and second transistors, and b1 and b2 are the respective betas of said first and second transistors, wherein two of said circuits are connected in cascade by connection of the output terminal of the first circuit and input terminal of the second circuit to a common external constant current circuit.
Claim 9
Dependent Claim
32 words
The invention in accordance with claim 6, wherein the junction areas of the transistors and diodes of one circuit are chosen 1/k times the respective corresponding junction areas in the other circuit.
Claim 10
Dependent Claim
203 words
In combination, first and second transistors of opposite polarity types, each including collector, base and emitter elements, first and second semiconductor diodes, each including two elements, and interconnecting means coupled to the elements of said transistors and diodes for forming a three terminal circuit, said interconnecting means being constructed and arranged such that the collector of said first transistor is coupled to a first element of said second diode and the collector of said second transistor is coupled to a first element of said first diode, the emitter of said first transistor and a second element of said first diode are each coupled substantially directly to a first terminal of said three terminal circuit, the emitter of said second transistor is coupled to a second terminal of said three terminal circuit, and a second element of said second diode is coupled to a third terminal of said three terminal circuit, wherein said three terminal circuit comprises only semiconductors and no resistors, capacitors or inductors, wherein first and second ones of said circuits are connected in cascade, the first terminals of said circuits being coupled together and the third terminal of the first circuit being coupled to the second terminal of the second circuit.
Claim 11
Dependent Claim
203 words
In combination, first and second transistors of opposite polarity types, each including collector, base and emitter elements, first and second semiconductor diodes, each including two elements, and interconnecting means coupled to the elements of said transistors and diodes for forming a three terminal circuit, said interconnecting means being constructed and arranged such that the collector of said first transistor is coupled to a first element of said second diode and the collector of said second transistor is coupled to a first element of said first diode, the emitter of said first transistor and a second element of said first diode are each coupled substantially directly to a first terminal of said three terminal circuit, the emitter of said second transistor is coupled to a second terminal of said three terminal circuit, and a second element of said second diode is coupled to a third terminal of said three terminal circuit, wherein said three terminal circuit comprises only semiconductors and no resistors, capacitors or inductors, wherein first and second ones of said circuits are connected in cascade, the first terminals of said circuits being coupled together and the third terminal of the first circuit being coupled to the second terminal of the second circuit.
Claim 12
Dependent Claim
71 words
The invention in accordance with claim 8, wherein a power source is coupled to said first terminals, wherein a voltage to be regulated is coupled to the second terminal of sAid first circuit, wherein a coupling resistor is coupled to the third terminal of said first circuit and the second terminal of said second circuit, and wherein a reference voltage source is coupled to the third terminal of said second circuit.
Claim 13
Dependent Claim
17 words
The invention in accordance with claim 9, wherein said transistors and diodes are provided integrated circuit form.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-01 | 1976-01-31 | 1976-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-01 | 1980-01-31 | 1980-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-01 | 1984-01-31 | 1984-08-01 | $7700.00 | Window Closed / Lapsed |