Method and apparatus for testing and diagnosing data processing circuitry

Claim 2

In an automatically performable, electronically implemented method of testing a network exhibiting a time-dependent error and constructed and arranged for operation in response to applied clock signals, the steps of: repeatedly applying input data and a predetermined plurality of clock signals to said network with a different clock period being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; checking the correctness of operation of said network for each application of said input data and said predetermined plurality of clock signals; and determining the clock period during which said time-dependent error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock pulses which results in preventing occurrence of said error.

Claim 3

The invention in accordance with claim 1, wherein the step of checking comprises comparing the result provided by said network after application of said input data and said predetermined plurality of clock signals with the correct result which would be obtained if no error is present in the network.

Claim 4

The invention in accordance with claim 2, including the step of comparing the result provided by said network in the clock period immediately following the identified error clock period with the result that would be obtained if no error were present.

Claim 5

In an automatically performable, electronically implemented method of testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the steps of: determining the presence of a time-dependent error in said network; repeatedly applying input data and a predetermined plurality of clock signals to said network with a different selected one of the clock periods being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each clock period extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; checking the correctness of said at least one state of said network after each application of said input data and said predetermined plurality of clock signals; and determining the particular clock period during which said error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock signals which results in preventing occurrence of said error.

Claim 6

In an automatically performable, electronically implemented method of testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the steps of: determining the presence of a time-dependent error in said network; repeatedly applying input data and a predetermined plurality of clock signals to said network with a different selected one of the clock periods being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each clock period extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; checking the correctness of said at least one state of said network after each application of said input data and said predetermined plurality of clock signals; and determining the particular clock period during which said error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock signals which results in preventing occurrence of said error.

Claim 7

The invention in accordance with claim 4, including the steps of: deriving the error and correct states of said network in the clock period immediately following the identified error clock period; comparing the derived error and correct states of said network; and displaying the results of the comparison of said error and correct states.

Claim 8

The invention in accordance with claim 4, wherein the step of determining the presence of a time-dependent error comprises: applying said input data and said predetermined plurality of clock signals to said network without providing any clock period extensions and checking for the occurrence of an error in the result obtained; and again applying said input data and said predetermined plurality of clock signals to said network but at a reduced frequency sufficient to prevent occurrence of said error if it is of a time-dependent type.

Claim 9

In an automatically performable, electronically implemented method of testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the steps of: applying input data and a predetermined plurality of clock signals to said network at a first frequency during which said input data applied to said network is processed, the states of said network being indicative of the processing of said input data; checking the correctness of at least one state of said network after application thereto of said input data and said predetermined plurality of clock signals at said first frequency; in the event said checking indicates an error, applying said input data and said predetermined plurality of clock signals to said network at a significantly reduced clock frequency chosen to prevent occurrence of a time-dependent error; checking the correctness of said at least one state of said network after application thereto of said predetermined plurality of clock signals at said reduced frequency; in the event said checking at said reduced frequency indicates a correct result, repeating at least one more time the application of said predetermined plurality of clock signals to said network at said first frequency with a different selected one of the clock periods being extended during each such repeating by an amount sufficient to correct said error if it occurs during that clock period; checking the correctness of said at least one state of said network after each repeat operation; determining the particular clock period during which said error occurs based on a determination of which of the repeated applications of said input data and said predetermined plurality of clock signals to said network achieves a correct result; deriving the error and correct states of said network in the clock period immediately following the identified error clock period; and comparing the derived error and correct states of said network for use in diagnosing said network.

Claim 10

In an automatically performable, electronically implemented method of testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the steps of: applying input data and a predetermined plurality of clock signals to said network at a first frequency during which said input data applied to said network is processed, the states of said network being indicative of the processing of said input data; checking the correctness of at least one state of said network after application thereto of said input data and said predetermined plurality of clock signals at said first frequency; in the event said checking indicates an error, applying said input data and said predetermined plurality of clock signals to said network at a significantly reduced clock frequency chosen to prevent occurrence of a time-dependent error; checking the correctness of said at least one state of said network after application thereto of said predetermined plurality of clock signals at said reduced frequency; in the event said checking at said reduced frequency indicates a correct result, repeating at least one more time the application of said predetermined plurality of clock signals to said network at said first frequency with a different selected one of the clock periods being extended during each such repeating by an amount sufficient to correct said error if it occurs during that clock period; checking the correctness of said at least one state of said network after each repeat operation; determining the particular clock period during which said error occurs based on a determination of which of the repeated applications of said input data and said predetermined plurality of clock signals to said network achieves a correct result; deriving the error and correct states of said network in the clock period immediately following the identified error clock period; and comparing the derived error and correct states of said network for use in diagnosing said network.

Claim 11

The invention in accordance with claim 7, wherein said reduced frequency is chosen so that the resulting reduced frequency clock period is equal to an extended clock period at said first frequency.

Claim 12

The invention in accordance with claim 7, wherein the step of deriving said error and correct states comprises: applying said input data and said predetermined plurality of clock signals to said network at said first frequency without extension of the identified error clock period and storing the states of said network in the clock period immediately following the identified error clock period, whereby said error states are derived; and applying said input data and said predetermined plurality of clock signals to said network with the identified error clock period extended and storing the states of said network in the clock period immediately following the identified error clock period, whereby said correct states are derived.

Claim 13

The invention in accordance with claim 7, including the step of displaying the results of comparing said error and correct states of said network.

Claim 14

In a system for testing a network exhibiting a time-dependent error and constructed and arranged for operation in response to applied clock signals, the combination of: means for repeatedly applying input data and a predetermined plurality of clock signals to said network with a different clock period being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; means for checking the correctness of operation of said network for each application of said input data and said predetermined plurality of clock signals; and means for determining the clock period during which said time-dependent error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock pulses which results in preventing occurrence of said error.

Claim 15

In a system for testing a network exhibiting a time-dependent error and constructed and arranged for operation in response to applied clock signals, the combination of: means for repeatedly applying input data and a predetermined plurality of clock signals to said network with a different clock period being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; means for checking the correctness of operation of said network for each application of said input data and said predetermined plurality of clock signals; and means for determining the clock period during which said time-dependent error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock pulses which results in preventing occurrence of said error.

Claim 16

In a system for testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the combination of: means for determining the presence of a time-dependent error in said network; means for repeatedly applying input data and a predetermined plurality of clock signals to said network with a different selected one of the clock periods being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each clock period extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; checking the correctness of said at least one state of said network after each application of said input data and said predetermined plurality of clock signals; and means for determining the particular clock period during which said error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock signals which results in preventing occurrence of said error.

Claim 17

In a system for testing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the combination of: means for determining the presence of a time-dependent error in said network; means for repeatedly applying input data and a predetermined plurality of clock signals to said network with a different selected one of the clock periods being extended for each application of said input data and said predetermined plurality of clock signals, the amount of each clock period extension being chosen to prevent occurrence of a time-dependent error if it occurs during that clock period; checking the correctness of said at least one state of said network after each application of said input data and said predetermined plurality of clock signals; and means for determining the particular clock period during which said error occurs based on a determination of the particular application of said input data and said predetermined plurality of clock signals which results in preventing occurrence of said error.

Claim 18

The invention in accordance with claim 4, including: means for deriving the error and correct states of said network in the clock period immediately following the identified error clock period; means for comparing the derived error and correct states of said network; and means for displaying the results of the comparison of said error and correct states.

Claim 19

In a system for testing and diagnosing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the combination of: means for applying input data and a predetermined plurality of clock signals to said network at a first frequency during which said input data is processed, the states of said network being indicative of the processing of said input data; means for applying said predetermined plurality of clock signals to said network at a significantly reduced clock frequency chosen to prevent occurrence of a time-dependent error if present in said network; means for checking the correctness of said at least one state of said network after application thereto of said predetermined plurality of clock signals at said first frequency and after application thereto at said reduced frequency for determining the presence of a time-dependent error in said network; means for repeating the application of said predetermined plurality of clock signals to said network at said first frequency a predetermined number of times determined by the number of clock periods which are to be checked for occurrence of said error, each such repeating extending a different one of the clock periods by an amount sufficient to correct said error if it occurs during that clock period; means for determining the particular clock period during which said error occurs based on a determination of which of said repeated applications results in correction of said error; means for deriving the correct and error states of said network in the clock period immediately following the identified error clock period; and means for comparing said error and correct states and for indicating the results of this comparison.

Claim 20

In a system for testing and diagnosing a multi-state digital network constructed and arranged for operation in response to applied clock signals, the combination of: means for applying input data and a predetermined plurality of clock signals to said network at a first frequency during which said input data is processed, the states of said network being indicative of the processing of said input data; means for applying said predetermined plurality of clock signals to said network at a significantly reduced clock frequency chosen to prevent occurrence of a time-dependent error if present in said network; means for checking the correctness of said at least one state of said network after application thereto of said predetermined plurality of clock signals at said first frequency and after application thereto at said reduced frequency for determining the presence of a time-dependent error in said network; means for repeating the application of said predetermined plurality of clock signals to said network at said first frequency a predetermined number of times determined by the number of clock periods which are to be checked for occurrence of said error, each such repeating extending a different one of the clock periods by an amount sufficient to correct said error if it occurs during that clock period; means for determining the particular clock period during which said error occurs based on a determination of which of said repeated applications results in correction of said error; means for deriving the correct and error states of said network in the clock period immediately following the identified error clock period; and means for comparing said error and correct states and for indicating the results of this comparison.