Timing error detection circuit

Claim 2

In a communication switching system including at least one peripheral unit and a common control means for supplying data and commands to said peripheral unit, said peripheral unit including timing means responsive to a command provided by said common control means to generate a plurality of timing signals for sequencing the operation of said peripheral units, a method for detecting timing errors in said peripheral unit comprising: registering at least certain ones of said timing signals as said timing signals are generated during a given operation cycle, wherein registering said certain timing signals includes enabling a different latch circuit to provide a first output as each of said certain timing signals is generated whereby said latch circuits provide a first set of outputs whenever all of said certain timing signals are generated and a different set of outputs whenever one or more of said certain timing signals fails to be generated.

Claim 3

A method as set forth in claim 1 wherein determining that each of said certaIn timing signals has been generated includes combining the outputs of said latch circuits and enabling a further latch circuit when all of said latch circuits provide said first output.

Claim 4

A method as set forth in claim 2 wherein providing an error indication includes gating an output provided by said further latch circuit to enable an error circuit to provide an error signal.

Claim 5

A method as set forth in claim 3 which includes transmitting said error signal to said common control means.

Claim 6

In a communication switching system including at least one peripheral unit and a common control means for supplying data and commands to said peripheral unit, said peripheral unit including timing means responsive to a command provided by said common control means to generate a plurality of timing signals for sequencing the operation of said peripheral unit, a timing error detection arrangement comprising: timing signal register means for storing at least certain ones of said timing signals as said certain timing signals are generated during a given operating cycle of said peripheral unit, said timing signal register means comprises a plurality of first latch circuits including an individual latch circuit corresponding to each of said certain timing signals, each of said latch circuits being set in response to the generation of the corresponding timing signal, timing error means, and enabling means enabled during said given operating cycle for controlling said timing error means to provide an error indication whenever one or more of said certain timing signals fails to be generated during said given operations cycle of said peripheral unit.

Claim 7

In a communication switching system including at least one peripheral unit and a common control means for supplying data and commands to said peripheral unit, said peripheral unit including timing means responsive to a command provided by said common control means to generate a plurality of timing signals for sequencing the operation of said peripheral unit, a timing error detection arrangement comprising: timing signal register means for storing at least certain ones of said timing signals as said certain timing signals are generated during a given operating cycle of said peripheral unit, said timing signal register means comprises a plurality of first latch circuits including an individual latch circuit corresponding to each of said certain timing signals, each of said latch circuits being set in response to the generation of the corresponding timing signal, timing error means, and enabling means enabled during said given operating cycle for controlling said timing error means to provide an error indication whenever one or more of said certain timing signals fails to be generated during said given operations cycle of said peripheral unit.

Claim 8

A timing error detection arrangement as set forth in claim 5 wherein said timing error means comprises a second latch circuit which is set by said enabling means whenever all of said certain timing signals are generated during said given operating cycle.

Claim 9

A timing error detection arrangement as set forth in claim 6 wherein said enabling means comprises gating means having a plurality of inputs individually connected to outputs of said first latch circuits, a further input connected to an output of said timing means, and an output connected to a control input of said second latch circuit, said gating means being enabled by a further timing pulse provided by said timing means being enabled by a further timing. pulse provided by said timing means after said certain timing pulses have been generated.

Claim 10

A timing error detection arrangement as set forth in claim 7 wherein said timing means generates a signal for resetting said first and second latch circuits after each operating cycle.

Claim 11

A timing error detection arrangement as set forth in claim 8 which includes error indication means enabled by said timing error latch means to provide an error signal for transmission to said common control means.

Claim 12

A timing error detection arrangement as set forth in claim 5 wherein said first latch circuits are set by the leading edges of said certain timing pulses whereby a given first latch circuit remains reset whenever the corresponding timing signal is continuously generated.