Timing recovery circuit for digital data

Claim 2

A timing recovery circuit comprising means for receiving a timing component, means for generating a signal having a frequency varying in response to a control signal, means responsive to a difference between phase of the variable frequency signal and phase of the timing component for producing a control component, means responsive to cycle slips between the variable frequency signal and the timing component for producing a series of pulses having a polarity related to the sense of the cycle slips and having a repetition rate directly related to the rate of the cycle slips except when amplitude of the timing component falls below a predetermined value whereupon no pulses are produced, and means for combining the control component with the series of pulses into the control signal that adjusts the frequency of the signal from the generating means into synchronization with the timing component.

Claim 3

A timing recovery circuit in accordance with claim 1 wherein the means for producing the control component includes means for providing the control component with a polarity for reducing the difference between phase of the variable frequency signal and phase of the timing component.

Claim 4

A timing recovery circuit in accordance with claim 1 wherein the means for producing the control component includes means for providing the contol component with a polarity for stabilizing the difference between phase of the variable frequency signal and phase of the timing component.

Claim 5

A timing recovery circuit in accordance with claim 1 wherein the means for producing the series of pulses includes means for providing a uniform pulse polarity for reducing cycle slips.

Claim 6

A timing recovery circuit in accordance with claim 4 wherein the means for producing the control component includes means for providing the control component with a polarity for reducing the difference between phase of the variable frequency signal and phase of the timing component.

Claim 7

A timing recovery circuit in accordance with claim 4 wherein the means for producing the control component includes means for providing the control component with a polarity for stabilizing the difference between phase of the variable frequency signal and phase of the timing component.

Claim 8

A frequency-locked loop and phase-locked loop comprising, means for extracting timing information from a stream of baseband data signals, means for producing an adjustable frequency signal, means for determining and quantizing first and second beat frequency signals from the data signals and the adjustable frequency signals, the second beat frequency signal being out-of-phase with the first beat frequency signal, means for differentiating the first beat frequency signal into a differentiated signal, means for generating control pulses of uniform amplitude from the differentiated signal and the second beat frequency signal, and means for applying a control signal including a combination of the control pulses and the second beat frequency signal to the adjustable frequency producing means for reducing the frequency of the beat frequency signals and locking the loop in phase with the bits of the baseband data signals.

Claim 9

A frequency-locked loop and phase-locked loop comprising, means for extracting timing information from a stream of baseband data signals, means for producing an adjustable frequency signal, means for determining and quantizing first and second beat frequency signals from the data signals and the adjustable frequency signals, the second beat frequency signal being out-of-phase with the first beat frequency signal, means for differentiating the first beat frequency signal into a differentiated signal, means for generating control pulses of uniform amplitude from the differentiated signal and the second beat frequency signal, and means for applying a control signal including a combination of the control pulses and the second beat frequency signal to the adjustable frequency producing means for reducing the frequency of the beat frequency signals and locking the loop in phase with the bits of the baseband data signals.

Claim 10

A frequency-locked loop and phase-locked loop in accordance with claim 7 wherein the generating means comprise a multiplier responsive to the differentiated signal and the second beat frequency signal for producing the control pulses.

Claim 11

A frequency-locked loop and phase-locked loop in accordance with claim 7 wherein the applying means include a loop filter responsive to the control pulses and to the second beat frequency signal for producing the control signal.

Claim 12

A frequency-locked loop and phase-locked loop in accordance with claim 9 wherein the loop filter has a first gain slope for a predetermined band of frequencies and a second gain slope for frequencies outside of the predetermined band.

Claim 13

A frequency-locked loop and phase-locked loop in accordance with claim 7 wherein the generating means comprise means responsive to the differentiated signal and the second beat frequency signal for producing the control pulses having a polarity for adjusting the frequency of the producing means to the bit rate of the baseband data signals.

Claim 14

A frequency-locked loop and phase-locked loop in accordance with claim 11 wherein the responsive means produces pulses at a rate directly related to the difference between the bit rate and the frequency of the adjustable frequency signal.

Claim 15

A frequency-locked loop and a phase-locked loop in accordance with claim 11 wherein a lead feeds back the second beat frequency signal to the producing means for decreasing phase difference between the adjustable frequency signal and bits of the baseband data signals.

Claim 16

A frequency-locked loop and a phase-locked loop in accordance with claim 11 wherein a lead feeds back the second beat frequency signal to the producing means for stabilizing phase difference between the adjustable frequency signal and bits of the baseband data signals.

Claim 17

In combination a frequency-locked loop comprising means for receiving extracted timing signals; a first branch including in series circuit arrangement a first multiplier responsive to the extracted timing signals, a first low pass filter, a first comparator, a differentiator; a second branch including in series circuit arrangement a second multiplier responsive to the extracted timing signals, a second low pass filter, and a second comparator; a third multiplier responsive to the output of the differentiator and the output of the second comparator for producing cycle slip pulses; a third branch including in a series circuit arrangement a summing circuit responsive to the output of the third multiplier, a loop filter, a controlled oscillator, and a phase shifter having first and second phase outputs, means connecting the first phase output of the phase shifter to a second input of the first multiplier and the second phase output of the phase shifter to a second input of the second multiplier; and a phase-locked loop comprising the second multiplier and the second low pass filter, means for connecting the output of the second low pass filter to a second input of the summing circuit.

Claim 18

In combination a frequency-locked loop comprising means for receiving extracted timing signals; a first branch including in series circuit arrangement a first multiplier responsive to the extracted timing signals, a first low pass filter, a first comparator, a differentiator; a second branch including in series circuit arrangement a second multiplier responsive to the extracted timing signals, a second low pass filter, and a second comparator; a third multiplier responsive to the output of the differentiator and the output of the second comparator for producing cycle slip pulses; a third branch including in a series circuit arrangement a summing circuit responsive to the output of the third multiplier, a loop filter, a controlled oscillator, and a phase shifter having first and second phase outputs, means connecting the first phase output of the phase shifter to a second input of the first multiplier and the second phase output of the phase shifter to a second input of the second multiplier; and a phase-locked loop comprising the second multiplier and the second low pass filter, means for connecting the output of the second low pass filter to a second input of the summing circuit.

Claim 19

In combination a frequency-locked loop comprising means for receiving extracted timing signals; a first branch including in series circuit arrangement a first multiplier responsive to the extracted timing signals, a first low pass filter, a first comparator, a differentiator; a second branch including in series circuit arrangement a second multiplier responsive to the extracted timing signals, a second low pass filter, and a second comparator; a third multiplier responsive to the output of the differentiator and the output of the second comparator for producing cycle slip pulses; a third branch including in a series circuit arrangement a summing circuit responsive to the output of the third multiplier, a loop filter, a controlled oscillator, and a phase shifter having first and second phase outputs, means connecting the first phase output of the phase shifter to a second input of the first multiplier and the second phase output of the phase shifter to a second input of the second multiplier; and a phase-locked loop comprising a phase detector, a third low pass filter, means connecting the output of the third low pass filter to a second input of the summing circuit, means connecting an output of the phase shifter to a second input of the phase detector.

Claim 20

In combination a frequency-locked loop comprising means for receiving extracted timing signals; a first branch including in series circuit arrangement a first multiplier responsive to the extracted timing signals, a first low pass filter, a first comparator, a differentiator; a second branch including in series circuit arrangement a second multiplier responsive to the extracted timing signals, a second low pass filter, and a second comparator; a third multiplier responsive to the output of the differentiator and the output of the second comparator for producing cycle slip pulses; a third branch including in a series circuit arrangement a summing circuit responsive to the output of the third multiplier, a loop filter, a controlled oscillator, and a phase shifter having first and second phase outputs, means connecting the first phase output of the phase shifter to a second input of the first multiplier and the second phase output of the phase shifter to a second input of the second multiplier; and a phase-locked loop comprising a phase detector, a third low pass filter, means connecting the output of the third low pass filter to a second input of the summing circuit, means connecting an output of the phase shifter to a second input of the phase detector.