US3766484A
Expired / Lapsed
US
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Detection of cycle slippage between two signals
Assignee: AT&T Inc
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Filing: 1972-09-18
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Granted: 1973-10-16
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Expires: 1992-09-18
Abstract
Abstract Clocking signals are recovered from an incoming signal train by a master clock oscillator phase locked to the incoming signals, and, in the event of a failure or malfunction involving the master clock, by a standby clock similarly phase locked to the incoming signals. One of the malfunctions occurs when the phase of the clock output slips a cycle with respect to the phase of the signal train. It is determined that a cycle slippage condition exists when phase comparisons of the signals indicate the clock output is passing from a phase lag error to a phase lead error, or vice versa, without passing through a region of no phase error.
Inventors
- 👤 G Pasternack
- 👤 B Saltzberg
- 👤 R Morris
- 👤 O Napolitano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 02:11
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/07; H03K; H03K5/00; H03K5/22; H03K5/26; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
189 words
A circuit for detecting cycle slippage between two signals having approximately the same frequency comprising: comparing means responsive to the two signals for indicating when the two signals are substantially in phase, for indicating when one of the signals lags the other signal in phase and for indicating when the one signal leads the other signal in phase, and sequential logic means responsive to the comparing means for determining that the comparing means sequentially provided one and the other of the two indications that the one signal lags in phase and that the one signal leads in phase without providing an intervening indication that the signals are substantially in phase, wherein the sequential logic means has a plurality of states and includes digital logic means and memory means, the memory means being responsive to the digital logic means for storing therein a designation of a present state of the sequential logic means and the digital logic means being jointly responsive to the comparing means indication and the memory means present state designation for applying to the memory means a designation of a next state of the sequential logic means.
Claim 2
Dependent Claim
189 words
A circuit for detecting cycle slippage between two signals having approximately the same frequency comprising: comparing means responsive to the two signals for indicating when the two signals are substantially in phase, for indicating when one of the signals lags the other signal in phase and for indicating when the one signal leads the other signal in phase, and sequential logic means responsive to the comparing means for determining that the comparing means sequentially provided one and the other of the two indications that the one signal lags in phase and that the one signal leads in phase without providing an intervening indication that the signals are substantially in phase, wherein the sequential logic means has a plurality of states and includes digital logic means and memory means, the memory means being responsive to the digital logic means for storing therein a designation of a present state of the sequential logic means and the digital logic means being jointly responsive to the comparing means indication and the memory means present state designation for applying to the memory means a designation of a next state of the sequential logic means.
Claim 3
Dependent Claim
83 words
A circuit for detecting cycle slippage, as in claim 1, wherein the digital logic means is responsive to the comparing means indication that the one signal lags in phase for applying to the memory means a designation of a predetermined next one of the states and wherein the digital logic means further includes means jointly responsive to the memory means predetermined state designation and the comparing means indication that the one signal leads in phase for determining that a cycle slippage has occurred.
Claim 4
Dependent Claim
83 words
A circuit for detecting cycle slippage, as in claim 1, wherein the digital logic means is responsive to the comparing means indication that the one signal leads in phase for applying to the memory means a designation of a predetermined next one of the states and wherein the digital logic means further includes means jointly responsive to the memory means predetermined state designation and the comparing means indication that the one signal lags in phase for determining that a cycle slippage has occurred.
Claim 5
Dependent Claim
51 words
A circuit for detecting cycle slippage, as in claim 1, wherein the comparing means includes means for generating pulses, means for counting pulses, means responsive To the two signals for gating to the counting means the generated pulses and means for applying the generated pulse count to the digital logic means.
Claim 6
Dependent Claim
176 words
A circuit for detecting cycle slippage between two signals comprising: comparing means responsive to the two signals for indicating the magnitude of the phase difference between the two signals, first digital logic means responsive to the comparing means indication for designating in a memory means that the magnitude of the phase difference is less than a fixed threshold, that one of the signals lags the other signal in phase by a magnitude more than the fixed threshold and less than a predetermined greater magnitude, and that the one signal leads the other signal in phase by a magnitude more than the fixed threshold and less than the predetermined greater magnitude, and further digital logic means jointly responsive to the memory means designation that the one signal lags in phase and the comparing means indication that the one signal leads in phase and jointly responsive to the memory means designation that the one signal leads in phase and the comparing means indication that the one signal lags in phase for determining that a cycle slippage has occurred.
Claim 7
Dependent Claim
176 words
A circuit for detecting cycle slippage between two signals comprising: comparing means responsive to the two signals for indicating the magnitude of the phase difference between the two signals, first digital logic means responsive to the comparing means indication for designating in a memory means that the magnitude of the phase difference is less than a fixed threshold, that one of the signals lags the other signal in phase by a magnitude more than the fixed threshold and less than a predetermined greater magnitude, and that the one signal leads the other signal in phase by a magnitude more than the fixed threshold and less than the predetermined greater magnitude, and further digital logic means jointly responsive to the memory means designation that the one signal lags in phase and the comparing means indication that the one signal leads in phase and jointly responsive to the memory means designation that the one signal leads in phase and the comparing means indication that the one signal lags in phase for determining that a cycle slippage has occurred.
Claim 8
Dependent Claim
52 words
A circuit for detecting cycle slippage, as in claim 5, wherein the first digital logic means is jointly responsive to the memory means designation and a comparing means indication that the magnitude of the phase difference is more than the predetermined magnitude for redesignating in the memory means the memory means designation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |