Fade-in and fade-out switching circuit

Claim 1

A switching circuit comprising first and second semiconductor devices each including a semiconductor substrate having a current path portion, first and second semiconductor regions forming a PN-junction therebetween, said first region being capacitively coupled to said current path portion, a control electrode connected to said second region, first and second terminals electrically connected to both ends of said current path portion respectively, a signal input terminal electrically connected to said first terminal of said first semiconductor device, an output terminal electrically connected to said second terminal of said first semiconductor device, means for connecting said control electrode of said first semiconductor device to said first terminal of said second semiconductor device, means for applying a bias voltage to said second terminal of said second semiconductor device, switch means for selectively applying a bias voltage to said control electrode of said second semiconductor device and neutralization means operative on at least one of said first and second semiconductor devices for injecting carriers into said first region of said device to independently control a fade-in and fade-out time.