Field effect transistor having a pair of gate regions

Claim 2

A field effect transistor having a semiconductor layer of one conductivity type, source and drain regions at opposite ends of said layer, a first gate region in said layer of the opposite conductivity type defining a channel between said source and drain regions, a second gate region is said layer of said one conductivity type separated from said channel by said first gate region, there being a PN-junction between said first and second gate regions and a second PN-junction between said channel and said first gate region, whereby when said first PN-junction is reversely biased and electric charge is stored in said first gate region such that a time delay occurs in the drain current when being switched from off to on condition.

Claim 3

A semiconductor device comprising a semiconductor substrate having a current path portion between source and drain electrodes, first and second semiconductor regions forming a first PN-junction therebetween, said first region being capacitively coupled to said current path portion, a control terminal connected to said second region, whereby an electric charge is stored in said first region when said PN-junction is reversely biased, and a second PN-junction for coupling said first region to said current path portion such that a time delay occurs in the drain current when being switched from the off to on condition.

Claim 4

A semiconductor device comprising a semiconductor substrate having a current path portion between source and drain electrodes, first and second semiconductor regions forming a first PN-junction therebetween, said first region being capacitively coupled to said current path portion, a control terminal connected to said second region, whereby an electric charge is stored in said first region when said PN-junction is reversely biased, and a second PN-junction for coupling said first region to said current path portion such that a time delay occurs in the drain current when being switched from the off to on condition.

Claim 5

A semiconductor device according to claim 2, which includes an insulating layer for coupling said first region to said current path portion.

Claim 6

A semiconductor device according to claim 2, wherein said current path portion is of an opposite conductivity type to said first region.

Claim 7

A semiconductor device according to claim 4, which includes a third region of the same conductivity type as said first region, said third region being adjacent to said current path portion.

Claim 8

A semiconductor device according to claim 4, which includes a third region of the same conductivity type as said first region, said third region being adjacent to said second region.

Claim 9

A field effect tranSistor having a substrate of semiconductor material of one impurity type, and epitaxial layer of the opposite impurity type on one surface of said substrate, source and drain regions formed in the outer surface of said epitaxial layer of the same impurity type as said epitaxial layer but of relatively higher impurity concentration, a first gate region in said epitaxial layer of the opposite impurity type to said epitaxial layer, a second gate region superimposed on and formed in said first gate region of opposite impurity type to said first gate region, but of relatively higher impurity concentration, a gate control circuit connected between said source region and said second gate region, a resistor, a potential source connected in series with said resistor between said source and drain regions, and output terminals connected to opposite ends of said resistor such that a time delay occurs in the drain current when being switched from the off to on condition.

Claim 10

A field effect tranSistor having a substrate of semiconductor material of one impurity type, and epitaxial layer of the opposite impurity type on one surface of said substrate, source and drain regions formed in the outer surface of said epitaxial layer of the same impurity type as said epitaxial layer but of relatively higher impurity concentration, a first gate region in said epitaxial layer of the opposite impurity type to said epitaxial layer, a second gate region superimposed on and formed in said first gate region of opposite impurity type to said first gate region, but of relatively higher impurity concentration, a gate control circuit connected between said source region and said second gate region, a resistor, a potential source connected in series with said resistor between said source and drain regions, and output terminals connected to opposite ends of said resistor such that a time delay occurs in the drain current when being switched from the off to on condition.

Claim 11

A field effect transistor according to claim 7, in which said substrate is of relatively high impurity concentration, and in which there is an ohmic contact on the under surface of said substrate, a second potential source and a switch connecting said second potential source between said source region and said ohmic contact.

Claim 12

A field effect transistor according to claim 7, in which there is a transparent insulating layer overlying the upper surface of said epitaxial layer, there being windows through said insulating layer through which extend a source electrode, a gate electrode and a drain electrode into contact with said source region, said second gate region and said drain region respectively.

Claim 13

A semiconductor device having first, second, and third contiguous conductor regions, said contiguous regions being of opposite conductivity type, first and second PN junctions between said first and second regions and between said second and third regions, respectively, first and second terminals provided to said first region, means for biasing said second PN junction and determining the state of said second region, means for detecting the impedance between said first and second terminals determined by the state of said second region, said biasing means and said impedance means having first and second points correspond while the responding time from said first to second impedance point is substantially equal to the exciting time from said first to second biasing point and the responding time from said second to first impedance point is longer than than exciting time from said second to first biasing point.

Claim 14

A semiconductor device having first, second, and third contiguous conductor regions, said contiguous regions being of opposite conductivity type, first and second PN junctions between said first and second regions and between said second and third regions, respectively, first and second terminals provided to said first region, means for biasing said second PN junction and determining the state of said second region, means for detecting the impedance between said first and second terminals determined by the state of said second region, said biasing means and said impedance means having first and second points correspond while the responding time from said first to second impedance point is substantially equal to the exciting time from said first to second biasing point and the responding time from said second to first impedance point is longer than than exciting time from said second to first biasing point.

Claim 15

A semiconductor device according to claim 10, wherein said first and second biasing points are reversely and forwardly biased, respectively.

Claim 16

A semiconductor device according to claim 10, wherein said second region stores charges therein at said first biasing point.