Patent US4989177A successfully refreshed from Google Patents.
Patent US4006046A successfully refreshed from Google Patents.
US4006046A
Expired / Lapsed
US
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Method for compensating for emitter-push effect in the fabrication of transistors
Assignee: Motorola Solutions Inc
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Filing: 1975-04-21
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Granted: 1977-02-01
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Expires: 1995-04-21
Abstract
Abstract A semiconductor wafer having a base dopant source disposed on its surface receives a surface coating consisting of, for example, a silicon nitride film. An emitter opening is formed in the silicon nitride surface coating and a portion of the base dopant source is stripped away within the emitter opening. Diffusion of the base region will result in predetermined geometrical regions of varying concentration of the base dopant as a result of the surface coating and the effect of the oxidizing atmosphere. Subsequent deposition and diffusion of the emitter region provides for smaller base widths and eliminates the need for subsequent deposition and diffusion of high concentration base dopant contact regions.
Inventors
- 👤 Pravin C. Parekh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:48
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10D; H10D99/00; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662; H10P14/68; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/694; H10P14/6943; H10P14/69433; H10P32/00; H10P32/10; H10P32/14; H10P32/17; H10P32/171; H10P95/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
195 words
A method for fabricating an electrical translating device comprising the steps of: a. providing a semiconductor wafer of a first conductivity type; b. disposing a first passivating layer on the surface of said semiconductor wafer; c. forming an opening in said first passivating layer exposing a portion of the surface of said semiconductor wafer; d. disposing a first dopant layer of a second conductivity type opposite to said first conductivity type at least within said opening; e. disposing a second passivating nitride layer upon said first dopant layer; f. forming an opening in said second passivating layer which is smaller than the opening in said first passivating layer exposing a portion of said first dopant layer; g. removing a uniform portion of said exposed first dopant layer; and h. diffusing a first dopant from said first dopant layer into said semiconductor wafer and forming a first and second concentration region of said first dopant, said first concentration region being beneath said second passivating layer and having a greater concentration of said first dopant than said second concentration region of said semiconductor wafer, said second concentration region being beneath said opening in said second passivating layer.
Claim 2
Independent Claim
195 words
A method for fabricating an electrical translating device comprising the steps of: a. providing a semiconductor wafer of a first conductivity type; b. disposing a first passivating layer on the surface of said semiconductor wafer; c. forming an opening in said first passivating layer exposing a portion of the surface of said semiconductor wafer; d. disposing a first dopant layer of a second conductivity type opposite to said first conductivity type at least within said opening; e. disposing a second passivating nitride layer upon said first dopant layer; f. forming an opening in said second passivating layer which is smaller than the opening in said first passivating layer exposing a portion of said first dopant layer; g. removing a uniform portion of said exposed first dopant layer; and h. diffusing a first dopant from said first dopant layer into said semiconductor wafer and forming a first and second concentration region of said first dopant, said first concentration region being beneath said second passivating layer and having a greater concentration of said first dopant than said second concentration region of said semiconductor wafer, said second concentration region being beneath said opening in said second passivating layer.
Claim 3
Dependent Claim
64 words
A method for fabricating an electrical translating device as defined in claim 1 further including the steps of: a. disposing a second dopant layer of said first conductivity type at least within the opening in said second passivating layer; and b. diffusing a second dopant from said dopant layer into said semiconductor wafer within at least said second concentration region of said semiconductor wafer.
Claim 4
Dependent Claim
30 words
A method for fabricating an electrical translating device as defined in claim 2 wherein said second dopant is diffused into said semiconductor wafer substantially within the lower concentration region thereof.
Claim 5
Dependent Claim
48 words
A method for fabricating an electrical translating device as defined in claim 1 further comprising the steps of: a. forming an opening in said second passivating layer exposing the surface of said semiconductor wafer; and b. making electrical contact to said first concentration region of said semiconductor wafer.
Claim 6
Independent Claim
240 words
A method in the fabrication of a transistor comprising the steps of: a. providing a silicon wafer of a first conductivity type; b. disposing a first passivating layer on the surface of said first semiconductor wafer; c. forming a base opening in said first passivating layer thereby exposing a portion of the surface of said semiconductor wafer; d. disposing a base dopant layer at least within said base opening, said base dopant layer having a second conductivity type opposite to said first conductivity type; e. disposing a layer of silicon nitride upon said base dopant layer; f. forming an emitter opening and a base contact opening in said silicon nitride layer, said emitter opening and said base contact opening being within the boundary of said base opening; g. disposing a second passivating layer upon and covering said emitter and base contact openings; h. exposing said base dopant layer within said emitter opening by selectively removing a portion of said second passivating layer; i. removing a uniform portion of said exposed base dopant layer; and j. diffusing a base of dopant from said base dopant layer into said silicon wafer and forming a first concentration region of said base dopant beneath said silicon nitride and second passivating layer having a greater concentration of said base dopant than a second concentration region of said base dopant formed beneath said emitter opening, said first and second concentration regions forming a base dopant region.
Claim 7
Independent Claim
240 words
A method in the fabrication of a transistor comprising the steps of: a. providing a silicon wafer of a first conductivity type; b. disposing a first passivating layer on the surface of said first semiconductor wafer; c. forming a base opening in said first passivating layer thereby exposing a portion of the surface of said semiconductor wafer; d. disposing a base dopant layer at least within said base opening, said base dopant layer having a second conductivity type opposite to said first conductivity type; e. disposing a layer of silicon nitride upon said base dopant layer; f. forming an emitter opening and a base contact opening in said silicon nitride layer, said emitter opening and said base contact opening being within the boundary of said base opening; g. disposing a second passivating layer upon and covering said emitter and base contact openings; h. exposing said base dopant layer within said emitter opening by selectively removing a portion of said second passivating layer; i. removing a uniform portion of said exposed base dopant layer; and j. diffusing a base of dopant from said base dopant layer into said silicon wafer and forming a first concentration region of said base dopant beneath said silicon nitride and second passivating layer having a greater concentration of said base dopant than a second concentration region of said base dopant formed beneath said emitter opening, said first and second concentration regions forming a base dopant region.
Claim 8
Dependent Claim
83 words
A method as defined in claim 5 further including the steps of: a. disposing an emitter dopant layer of said first conductivity type at least within the emitter opening; and b. diffusing a second dopant from said emitter dopant layer into said silicon wafer within said base dopant region whereby the diffusion front of said second dopant pushes the dopant distribution of said second concentration region before it to produce a substantially uniform boundary between said base dopant region and said silicon wafer.
Claim 9
Dependent Claim
29 words
A method as defined in claim 6 wherein said second dopant from said emitter dopant layer is diffused within said base dopant region substantially within, said second concentration region.
Claim 10
Dependent Claim
67 words
A method as defined in claim 5 wherein said step of diffusing said second dopant from said base dopant layer comprises the steps of sequentially heating said silicon wafer at a temperature of approximately 1025° C for 20 minutes in an atmosphere of dry oxygen followed by heating said silicon wafer at a temperature of approximately 1025° C for 4 minutes in an atmosphere of hydrated oxygen.
Claim 11
Independent Claim
217 words
A method in the fabrication of a transistor comprising the steps of: a. providing a silicon wafer of N-type conductivity having a first passivating surface layer disposed thereon; b. forming a base region opening in said first passivating layer; c. disposing a base dopant layer of P-type conductivity at least within said base region opening; d. disposing a layer of silicon nitride upon said base region dopant layer; e. forming an emitter opening and a plurality of base contact openings in said silicon nitride layer within the boundary of said base region opening whereby the base dopant layer within said emitter opening and said base contact openings are exposed; f. disposing a layer of tetraethylorthosilicate at least upon and covering the base dopant layer exposed by said emitter and base contact openings; g. etching said tetraethylorthosilicate layer within the boundary defined by said emitter opening whereby said base dopant layer is exposed; h. removing uniform portions of the base dopant layer exposed within the boundary of said emitter opening; and i. diffusing a base dopant from said base dopant layer into said silicon wafer, to form a base dopant distribution region beneath said emitter opening, said base dopant distribution region being diffused to a shallower depth than the base dopant beneath said silicon nitride and tetraethylorthosilicate layers.
Claim 12
Independent Claim
217 words
A method in the fabrication of a transistor comprising the steps of: a. providing a silicon wafer of N-type conductivity having a first passivating surface layer disposed thereon; b. forming a base region opening in said first passivating layer; c. disposing a base dopant layer of P-type conductivity at least within said base region opening; d. disposing a layer of silicon nitride upon said base region dopant layer; e. forming an emitter opening and a plurality of base contact openings in said silicon nitride layer within the boundary of said base region opening whereby the base dopant layer within said emitter opening and said base contact openings are exposed; f. disposing a layer of tetraethylorthosilicate at least upon and covering the base dopant layer exposed by said emitter and base contact openings; g. etching said tetraethylorthosilicate layer within the boundary defined by said emitter opening whereby said base dopant layer is exposed; h. removing uniform portions of the base dopant layer exposed within the boundary of said emitter opening; and i. diffusing a base dopant from said base dopant layer into said silicon wafer, to form a base dopant distribution region beneath said emitter opening, said base dopant distribution region being diffused to a shallower depth than the base dopant beneath said silicon nitride and tetraethylorthosilicate layers.
Claim 13
Dependent Claim
89 words
A method as defined in claim 9 further including the steps of: a. disposing an emitter dopant region of N-type conductivity at least within the emitter opening defined in said silicon nitride and tetraethylorthosilicate layers; and b. diffusing an emitter dopant from said emitter dopant layer into said silicon wafer within said base dopant distribution region whereby the diffusion front of said emitter dopant pushes the distribution of said base dopant before it to produce a substantially uniform boundary between said base dopant distribution region and said silicon wafer.
Claim 14
Dependent Claim
49 words
A method as defined in claim 9 wherein said diffusing steps forms a first concentration region of said base dopant beneath the silicon nitride and tetraethylorthosilicate layers which has a greater concentration of said base dopant than a second concentration region of said base dopant beneath said emitter opening.
Claim 15
Dependent Claim
26 words
A method as defined in claim 11 wherein said emitter dopant region is diffused within said base depant distribution region substantially within said second concentration region.
Claim 16
Dependent Claim
63 words
A method as defined in claim 9 wherein said step of diffusing said base dopant layer comprises the steps of sequentially heating said silicon wafer at a temperature of approximately 1025° C for 20 minutes in an atmosphere of dry oxygen followed by heating said silicon wafer at a temperature of approximately 1025° C for 4 minutes in an atmosphere of hydrated oxygen.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-01 | 1980-08-02 | 1981-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-01 | 1984-08-02 | 1985-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-01 | 1988-08-02 | 1989-02-01 | $7700.00 | Window Closed / Lapsed |