Patent US3991322A successfully refreshed from Google Patents.
US3991322A
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Signal delay means using bucket brigade and sample and hold circuits
Assignee: California Microwave Inc
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Filing: 1975-06-30
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Granted: 1976-11-09
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Expires: 1995-06-30
Abstract
Abstract A signal delay apparatus for delaying an information signal and including a bucket brigade device for sampling the signal and time delaying the samples, a sample-and-hold device for sampling and storing the voltage levels of the individual delayed samples in succession, and a clock for developing timing signals for controlling the delay line and the sample-and-hold device.
Inventors
- 👤 John A. Bush
- 👤 Michael Alexander Boutte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:34
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; G; G11; G11C; G11C11/00; G11C11/21; G11C11/24; G11C11/34; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/186; G11C19/28; G11C27/00; G11C27/02; G11C27/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
186 words
Apparatus for time delaying an input analog information signal comprising: clock means for generating a first timing signal including a series of first pulses, and a second timing signal including a series of second pulses, said second pulses being 180° out of phase with said first pulses; pulse stretching means for expanding the duration of said second pulses to provide a series of stretched pulses having leading edges substantially time coincident with the leading edges of said second pulses, and trailing edges delayed relative to those of said second pulses; bucket brigade delay line means responsive to said first pulses and said stretched pulses and operative to sample successive segments of the input analog information signal and to generate a train of voltage pulses corresponding to said segments and having voltage amplitudes proportional thereto, said voltage pulses being time delayed relative to the corresponding information signal segments; and sample-and-hold means responsive to said second pulses and operative to sample each of said voltage pulses and to reconstruct an analog signal which is an approximation of the input analog information signal delayed by a predetermined time period.
Claim 2
Dependent Claim
186 words
Apparatus for time delaying an input analog information signal comprising: clock means for generating a first timing signal including a series of first pulses, and a second timing signal including a series of second pulses, said second pulses being 180° out of phase with said first pulses; pulse stretching means for expanding the duration of said second pulses to provide a series of stretched pulses having leading edges substantially time coincident with the leading edges of said second pulses, and trailing edges delayed relative to those of said second pulses; bucket brigade delay line means responsive to said first pulses and said stretched pulses and operative to sample successive segments of the input analog information signal and to generate a train of voltage pulses corresponding to said segments and having voltage amplitudes proportional thereto, said voltage pulses being time delayed relative to the corresponding information signal segments; and sample-and-hold means responsive to said second pulses and operative to sample each of said voltage pulses and to reconstruct an analog signal which is an approximation of the input analog information signal delayed by a predetermined time period.
Claim 3
Dependent Claim
43 words
Apparatus as recited in claim 1 wherein said clock means includes a first multivibrator for generating said first timing signal and a second multivibrator for generating said second timing signal, said first and second multivibrators being driven by a common input signal source.
Claim 4
Dependent Claim
38 words
Apparatus as recited in claim 1 wherein said sample-and-hold means includes a voltage storage element and a sampling gate driven by said second timing signal and operative to successively gate said voltage pulses into said voltage storage element.
Claim 5
Dependent Claim
43 words
Apparatus as recited in claim 3 wherein said clock means includes a first multivibrator for generating said first timing signal and a second multivibrator for generating said second timing signal, said first and second multivibrators being driven by a common input signal source.
Claim 6
Dependent Claim
85 words
Apparatus as recited in claim 3 wherein said phase stretcher means includes an amplifier having input circuitry including a series-connected resistor, a shunt-connected capacitor and a diode connected in parallel with said resistor, said diode being polarized such that the energy of said second timing pulses charges said capacitor independent of said resistor but causes discharge of said capacitor through said resistor thereby delaying the trailing edges of the pulses according to the RC time constant of the combination of said resistor and said capacitor.
Claim 7
Dependent Claim
47 words
Apparatus as recited in claim 1 wherein said sample-and-hold means includes a sampling gate and a voltage storage element for successively storing said voltage pulses as they are gated thereinto by said sampling gate and for continuously outputting the stored voltages to develop said reconstructed analog signal.
Claim 8
Dependent Claim
159 words
A signal delay circuit comprising: means for generating a first train of regularly spaced pulses of a first duration, a second train of regularly spaced pulses of the same duration as said first pulses but shifted in time by 180° relative thereto, and a third train of regularly spaced pulses of longer duration than said second pulses but having their leading edges substantially time coincident with said second pulses; a bucket brigade delay line responsive to said first and third pulses and operative to generate voltage pulses corresponding to segments of an input information signal and having voltage amplitudes proportional to said segments, said voltage pulses being time delayed relative to corresponding segments of said information signal; and an output device including a sample-and-hold means responsive to said second pulses and operative to sample said voltage pulses and to reconstruct therefrom an analog signal which is an approximation of the input information signal delayed by a predetermined time period.
Claim 9
Dependent Claim
159 words
A signal delay circuit comprising: means for generating a first train of regularly spaced pulses of a first duration, a second train of regularly spaced pulses of the same duration as said first pulses but shifted in time by 180° relative thereto, and a third train of regularly spaced pulses of longer duration than said second pulses but having their leading edges substantially time coincident with said second pulses; a bucket brigade delay line responsive to said first and third pulses and operative to generate voltage pulses corresponding to segments of an input information signal and having voltage amplitudes proportional to said segments, said voltage pulses being time delayed relative to corresponding segments of said information signal; and an output device including a sample-and-hold means responsive to said second pulses and operative to sample said voltage pulses and to reconstruct therefrom an analog signal which is an approximation of the input information signal delayed by a predetermined time period.
Claim 10
Dependent Claim
40 words
A signal delay circuit as recited in claim 7 wherein said sample-and-hold means includes a voltage storage element and a sampling gate driven by said second pulses and operative to successively gate said voltage pulses into said voltage storage element.
Claim 11
Dependent Claim
50 words
A signal delay circuit as recited in claim 7 wherein said sample-and-hold means includes a sampling gate and a voltage storage element for successively storing said voltage pulses as they are gated thereto by said sampling gate and for continuously outputting the stored voltages to develop the reconstructed analog signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-11-09 | 1980-05-10 | 1980-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-11-09 | 1984-05-10 | 1984-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-11-09 | 1988-05-10 | 1988-11-09 | $7700.00 | Window Closed / Lapsed |