Silicon gate MOS device and method

Claim 1

In an MOS semiconductor device, a semiconductor body of first conductivity type having a planar surface, said body having spaced grooves therein opening through said surface, insulating material filling said grooves and extending to the planar surface of said body to form in combination with said body surface a continuous planar surface substantially free of physical step heights, spaced source and drain regions of second conductivity type formed in the body and extending to the surface in areas between said grooves filled with insulating material and providing a channel region therebetween, a relatively thin insulating layer formed on said surface and having a portion of relatively uniform thickness overlying the channel region, said thin insulating layer having substantially planar top and bottom surfaces, a layer of semiconductor material formed on a portion of said insulating layer, the bottom of said semiconductor layer having a planar surface, said semiconductor layer being delineated to form gate electrode portions overlying said channel region and further portions providing an interconnecting layer of uniform topography, a protective layer formed on said insulating layer and said layer of semiconductor material, and lead means formed on said protective layer and extending through said protective layer to contact said source and drain regions and said semiconductor layer.