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US3979730A
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US
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Interface adaptor having control register
Assignee: Motorola Solutions Inc
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Filing: 1974-10-30
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Granted: 1976-09-07
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Expires: 1994-10-30
Abstract
Abstract A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to a control register, the data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.
Inventors
- 👤 Thomas H. Bennett
- 👤 Earl F. Carlow
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
74 words
In an interface circuit coupled to a data bus and a peripheral data bus, said data bus and said peripheral data bus being bidirectional, circuitry comprising control register means coupled to said data bus and said peripheral data bus for controlling, under program control by a separate processor, a direction of data on a conductor of said peripheral data bus irrespectively of a direction of data on another conductor of said peripheral data bus.
Claim 2
Dependent Claim
74 words
In an interface circuit coupled to a data bus and a peripheral data bus, said data bus and said peripheral data bus being bidirectional, circuitry comprising control register means coupled to said data bus and said peripheral data bus for controlling, under program control by a separate processor, a direction of data on a conductor of said peripheral data bus irrespectively of a direction of data on another conductor of said peripheral data bus.
Claim 3
Dependent Claim
29 words
Circuitry as recited in claim 1 wherein the number of data conductors in said peripheral data bus is greater than the number of data conductors in said data bus.
Claim 4
Dependent Claim
71 words
Circuitry as recited in claim 1, including first circuit means coupled to said data bus, second circuit means coupled to said peripheral data bus, control circuit means coupled to said first and second circuit means for controlling bidirectional data transfers between said data bus and said peripheral data bus, said control circuit means also coupled to said control register means for controlling said control register means during said bidirectional data transfers.
Claim 5
Dependent Claim
47 words
Circuitry as recited in claim 3 wherein said first circuit means includes a plurality of data bus buffer circuits each including a receiving means and a transmitting means, each receiving means and transmitting means coupled, respectively, to a respective one of said conductors of said data bus.
Claim 6
Dependent Claim
16 words
Circuitry as recited in claim 1 wherein each of said transmitting means is a three-state inverter.
Claim 7
Dependent Claim
31 words
Circuitry as recited in claim 3 wherein first circuit means includes an input register including a plurality of input register flip-flops for temporary storage of data bits received from said processor.
Claim 8
Dependent Claim
32 words
Circuitry as recited in claim 5 wherein said first circuit means includes an input register including a plurality of input register flip-flops for temporary storage of data bits received from said processor.
Claim 9
Dependent Claim
44 words
Circuitry as recited in claim 3 wherein said second circuit means includes a plurality of peripheral data bus buffer circuits each including a receiving inverter and a transmitting inverter, each coupled, respectively, to a respective one of said conductors of said peripheral data bus.
Claim 10
Dependent Claim
36 words
Circuitry as recited in claim 1 further including a data register coupled between said data bus and said peripheral data bus for storage of information being transmitted to a perpheral unit coupled to said interface circuit.
Claim 11
Dependent Claim
34 words
Circuitry as recited in claim 5 wherein said control circuit means includes chip select, register select and read/write logic circuitry for generating required selection and read/write control signals required by a data processing sequence.
Claim 12
Dependent Claim
34 words
Circuitry as recited in claim 1 wherein said control register means includes a plurality of control registers for the storage of control information for controlling a sequence of data transfers in said interface circuit.
Claim 13
Independent Claim
117 words
A method of operating an interface circuit in a data processing system comprising the steps of: loading digital information into a control register of said interface circuit from a first data bus coupled to said interface circuit; utilizing said digital information to control a direction of data on a second data bus coupled to said interface circuit and also coupled to a peripheral unit, the direction of data transfer on each conductor of said second data bus being separately controlled by said digital information; reading the status of said control register by transferring information representative of said loaded digital information to said first data bus upon request by a processor means coupled to said first data bus.
Claim 14
Independent Claim
117 words
A method of operating an interface circuit in a data processing system comprising the steps of: loading digital information into a control register of said interface circuit from a first data bus coupled to said interface circuit; utilizing said digital information to control a direction of data on a second data bus coupled to said interface circuit and also coupled to a peripheral unit, the direction of data transfer on each conductor of said second data bus being separately controlled by said digital information; reading the status of said control register by transferring information representative of said loaded digital information to said first data bus upon request by a processor means coupled to said first data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-09-07 | 1980-03-08 | 1980-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-09-07 | 1984-03-08 | 1984-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-09-07 | 1988-03-08 | 1988-09-07 | $7700.00 | Window Closed / Lapsed |