Communication control device utilized as an input/output module for a remote terminal system

Claim 3

The method of claim 1 further comprising the steps of generating a second control signal by said communications control means in response to a control signal from said addressed device signaling that it is ready to execute a data transfer operation, and transferring said data characters between said one of said devices and communication control means during said data time intervals in response to said second control signal in accordance with said request under the control of said scanning means.

Claim 4

The method of claim 2 further comprising the step of automatically segmenting into blocks data characters transferred between said one of said data handling devices and said communications channel during said data transfer operation when said communication control means has detected that a predetermined number of characters constituting a block have been transmitted in the absence of a transmission of a character having a predetermined bit pattern.

Claim 5

A data processing terminal system including a bus, a plurality of data handling devices, a plurality of addressable device control means coupled to said bus, each of said addressable control means being adapted to respond to a respective address code for interconnecting at least one of said devices for a transfer of data characters between said bus and said one device, and device scanning means coupled to said bus for generating different address codes, each of the plurality of said address codes corresponding to a coded address of a different one of said plurality of said addressable control means, and said scanning means including means for generating on said bus control signals defining address and data time intervals for indicating respectively the application of address codes and data characters to said bus, said system further including an addressable communications control means coupled to said bus for interconnecting said system to a communications channel, said scanning means being operative to generate a predetermined address code corresponding to a coded address of said communications control means and said communications control means comprising: receive control means coupled to said communications channel, said receive control means including means for receiving a request including an address code designating one of said addressable device control means from said channel and means for storing a representation of said request; bus control means coupled to said receive control means and to said bus, said bus control means including first means conditioned by said stored representation to sample said bus during said address time intervals for said predetermined address code corresponding to said coded address of a said communications control means and in response thereto generate a first signal and second means responsive to said first signal to inhibit said scanning means from applying said data time interval control signals to said bus, and said bus control means further including logiC means operative during a subsequent address time interval to supply to said bus the address code corresponding to one of said addressable device control means of a selected one of said devices for initiating a data transfer operation in accordance with said request.

Claim 6

A data processing terminal system including a bus, a plurality of data handling devices, a plurality of addressable device control means coupled to said bus, each of said addressable control means being adapted to respond to a respective address code for interconnecting at least one of said devices for a transfer of data characters between said bus and said one device, and device scanning means coupled to said bus for generating different address codes, each of the plurality of said address codes corresponding to a coded address of a different one of said plurality of said addressable control means, and said scanning means including means for generating on said bus control signals defining address and data time intervals for indicating respectively the application of address codes and data characters to said bus, said system further including an addressable communications control means coupled to said bus for interconnecting said system to a communications channel, said scanning means being operative to generate a predetermined address code corresponding to a coded address of said communications control means and said communications control means comprising: receive control means coupled to said communications channel, said receive control means including means for receiving a request including an address code designating one of said addressable device control means from said channel and means for storing a representation of said request; bus control means coupled to said receive control means and to said bus, said bus control means including first means conditioned by said stored representation to sample said bus during said address time intervals for said predetermined address code corresponding to said coded address of a said communications control means and in response thereto generate a first signal and second means responsive to said first signal to inhibit said scanning means from applying said data time interval control signals to said bus, and said bus control means further including logiC means operative during a subsequent address time interval to supply to said bus the address code corresponding to one of said addressable device control means of a selected one of said devices for initiating a data transfer operation in accordance with said request.

Claim 7

The system of claim 4 wherein said device scanning means further includes timing means for generating signals defining alternately occurring ON-LINE and OFF-LINE bus cycle intervals, said bus control means being conditioned to monitor said bus and transfer characters between said bus and said communication control means only during address and data cycles corresponding to ON-LINE bus cycle intervals.

Claim 8

The system of claim 4 wherein said communications control means further includes memory means, said memory means including; first and second addressable memory storage means, each of said addressable storage means including a predetermined number of character storage locations, first and second programmable means, each being coupled to said first and second said storage means respectively for detecting when said storage means has been loaded with a predetermined number of characters and memory switching means, said switching means being coupled to said first and second memory storage means and to said bus control means, said memory switching means including means for sensing the availability of each of said memory storage means, said switching means being conditioned by said bus control means and said programmable means to switch memory storage means upon detecting when one of said memories is filled and the other of said memories is available whereby the writing of characters into one of said memory storage means and the reading of characters from the other of said memory storage means proceed simultaneously.

Claim 9

The system of claim 6 wherein each of said programmable means is operative to generate a first control signal indicating said corresponding memory storage means is full when said storage means associated therewith has been loaded with said predetermined number of characters and wherein said bus control means includes decoding means operative to generate a second control signal indicating said storage means is full in response to a character having a predetermined bit pattern being applied to said bus, said switching means being operative in response to said first control signal and in the absence of said second control signal to condition said memory storage means to transmit said characters in blocks each of which include said predetermined number of characters.

Claim 10

The system of claim 4 wherein said first means of said communications bus control means includes address decoding means operative to generate said first signal upon decoding said predetermined address code corresponding to an all ZERO coded addresss.

Claim 11

A remote data terminal system coupled to a communications line, said system comprising: a bus; a plurality of devices; a plurality of addressable control means, each of said addressable control means being coupled to said bus and to at least one of said devices for transferring characters between said bus and said device; line control means for transmitting and receiving characters to and from said communication line; first and second memory means selectively coupled to said bus and to said line control means, each of said memory means including a fixed maximum number of character storage locations, each location consisting of a fixed number of bit positions, each of said memory means further including memory address register means coupled for addressing storage locations in each said memory means and output register means coupled to transmit and receive characters to and from addressed storage locations of said memory means respectively; and, memory switching means coupled to said first and second memory means and to said bus, said memory switching means including means for selectively coupling said output register means of said first and sEcond memory means to transfer characters between said bus and said line control means, said memory switching means further including first sensing means coupled to said memory address register means of said first and second memory means for detecting when any one of said memory means has received and thereafter transmitted a predetermined number of characters and second sensing means for detecting the occurrence of a character having a predetermined bit pattern within the characters being transferred between said line control means and said bus, said memory switching means being operative in the absence of said second sensing means detecting said character to condition one of said memory means to receive up to said fixed maximum number characters from either said line control means or bus, said memory switching means further including logic means coupled to said first and second means and being conditioned by said first and second sensing means to generate a control signal to condition each of said memory means for switching and for transferring the contents of said one memory means alternately to said line control means and said bus in a manner so that transfer of characters between said first and second memory means and said line control means and bus respectively occur simultaneously and wherein said characters are blocked into segments whose length are defined by said predetermined number of characters in the absence of said sensing means detecting said character.

Claim 12

A remote data terminal system coupled to a communications line, said system comprising: a bus; a plurality of devices; a plurality of addressable control means, each of said addressable control means being coupled to said bus and to at least one of said devices for transferring characters between said bus and said device; line control means for transmitting and receiving characters to and from said communication line; first and second memory means selectively coupled to said bus and to said line control means, each of said memory means including a fixed maximum number of character storage locations, each location consisting of a fixed number of bit positions, each of said memory means further including memory address register means coupled for addressing storage locations in each said memory means and output register means coupled to transmit and receive characters to and from addressed storage locations of said memory means respectively; and, memory switching means coupled to said first and second memory means and to said bus, said memory switching means including means for selectively coupling said output register means of said first and sEcond memory means to transfer characters between said bus and said line control means, said memory switching means further including first sensing means coupled to said memory address register means of said first and second memory means for detecting when any one of said memory means has received and thereafter transmitted a predetermined number of characters and second sensing means for detecting the occurrence of a character having a predetermined bit pattern within the characters being transferred between said line control means and said bus, said memory switching means being operative in the absence of said second sensing means detecting said character to condition one of said memory means to receive up to said fixed maximum number characters from either said line control means or bus, said memory switching means further including logic means coupled to said first and second means and being conditioned by said first and second sensing means to generate a control signal to condition each of said memory means for switching and for transferring the contents of said one memory means alternately to said line control means and said bus in a manner so that transfer of characters between said first and second memory means and said line control means and bus respectively occur simultaneously and wherein said characters are blocked into segments whose length are defined by said predetermined number of characters in the absence of said sensing means detecting said character.

Claim 13

The terminal system of claim 9 further including receive control means coupled to said line control means for decoding characters received from said line and said logic means being coupled to be conditioned by said receive control means upon the decoding of an acknowledgment message from said line signaling a previous errorless transmission of data characters to generate said control signal when conditioned by either said first or second sensing means.

Claim 14

The terminal of claim 10 wherein said receive control means includes means operative upon decoding a message indicating that the transmission of said data characters as being in error to inhibit the generation of said control signal and to condition a predetermined one of said memory means to retransmit said characters previously transmitted.

Claim 15

The terminal system of claim 10 wherein said first sensing means includes programmable means for selecting different values for said predetermined number of characters which correspond to a number less than or equal to said maximum number of characters.

Claim 16

The terminal system of claim 12 wherein said programmable means includes jumper means coupled to said address register means of said first and second memory means for establishing a predetermined address and decoder means coupled to said jumper means, said decoder means being operative to generate a control signal for conditioning said logic means upon detecting that said address register means stores said predetermined address corresponding to said predetermined number of characters.

Claim 17

A terminal system comprising: a bus including a plurality of data and control lines; a plurality of peripheral devices; a plurality of addressable device control means, each of said control means being coupled to said bus and arranged for interconnecting at least one of said devices to transfer data characters between said device and said bus; device control scanning means coupled to said bus, said scanning means including addressing means for generating a plurality of different address codes on said bus, a number of said plurality of said address codes representing coded addresses of a particular class of said devices and said scanning means further including control means for generating bistate control signals for application to at least one of said control lines, different states of said control signals defining address and data intervals respectively for signaling when address codes and data characters are to be applied to said bus; And, an addressable communication control means coupled to said bus for interconnecting said bus to a communications channel, said communications means including: address decoding means for decoding a predetermined address code within said plurality of address codes generated by said scanning addressing means; control means coupled for said channel for receiving requests from said channel, said control means including means for storing a representation of said request, said means being coupled to said address decoding means for conditioning said decoding means to activate said communications means for a data transfer operation upon decoding of said predetermined address code; and, logic means coupled to said bus and to said control means for generating control signals for application to said control lines, said logic means being conditioned by said control means upon the activation of said communications means to apply said control signal to at least one of said control lines to selectively disable said device control scanning addressing means from addressing of any one of said addressable control means for activation of a device for a data transfer operation, said means of said control means selectively conditioning said communications control means to operate as either an input device or output device to transfer data characters between said channel and a designated one of said peripheral devices in accordance with said request.

Claim 18

A terminal system comprising: a bus including a plurality of data and control lines; a plurality of peripheral devices; a plurality of addressable device control means, each of said control means being coupled to said bus and arranged for interconnecting at least one of said devices to transfer data characters between said device and said bus; device control scanning means coupled to said bus, said scanning means including addressing means for generating a plurality of different address codes on said bus, a number of said plurality of said address codes representing coded addresses of a particular class of said devices and said scanning means further including control means for generating bistate control signals for application to at least one of said control lines, different states of said control signals defining address and data intervals respectively for signaling when address codes and data characters are to be applied to said bus; And, an addressable communication control means coupled to said bus for interconnecting said bus to a communications channel, said communications means including: address decoding means for decoding a predetermined address code within said plurality of address codes generated by said scanning addressing means; control means coupled for said channel for receiving requests from said channel, said control means including means for storing a representation of said request, said means being coupled to said address decoding means for conditioning said decoding means to activate said communications means for a data transfer operation upon decoding of said predetermined address code; and, logic means coupled to said bus and to said control means for generating control signals for application to said control lines, said logic means being conditioned by said control means upon the activation of said communications means to apply said control signal to at least one of said control lines to selectively disable said device control scanning addressing means from addressing of any one of said addressable control means for activation of a device for a data transfer operation, said means of said control means selectively conditioning said communications control means to operate as either an input device or output device to transfer data characters between said channel and a designated one of said peripheral devices in accordance with said request.

Claim 19

The system of claim 14 wherein said particular class of said devices are input devices.

Claim 20

The system of claim 14 wherein said predetermined address code corresponding to an all ZERO coded address.

Claim 21

The system of claim 14 wherein said device control scanning means further includes address and character response decoding means coupled to said bus, said response decoding means being operative in response to signals representative of device responses signaling acceptance of said address codes and data characters applied to said bus to generate control signals acknowledging receipt of said signals and wherein said logic means of said communication control means includes means operative to selectively apply a control signal to a predetermined one of said control lines for enabling said address and character response decoding means to generate said control signals when said communication control means applies one of said address codes to said bus to activate said designated one of said devices.

Claim 22

The system of claim 17 wherein said means of said logic means includes means for selectively switching said predetermined one of said control lines to first and second states to prevent the activation and to enable the activation respectively of said peripheral devices, said first and second states defining said bus as being in a busy and non busy state respectively.

Claim 23

The system of claim 17 wherein said device control scanning means includes timing means coupled to said response decoding means for generating signals defining alternately occurring ON-LINE and OFF-LINE bus cycle intervals, said address and character response decoding means being conditioned by said timing signals to decode said responses to said address codes only during said ON-LINE bus cycle intervals.

Claim 24

The system of claim 19 wherein said scanning means further includes decoding means coupled to said bus for decoding a character having a predetermined bit pattern and release control means coupled to said decoding means, and to said bus, said decoding means being operative upon decoding said character to selectively condition said release control means to apply signals to said bus to enable said device control scanning means to generate signals on said bus to release said device and reinitiate the generation of said address codes when enabled by said logic means.

Claim 25

The system of claim 20 wherein said addressable device control means coupled to each of said input peripheral devices includes release control means coupled to said bus and to said device Associated therewith, said release control means being conditioned by an out of media signal from said device indicating that said device has transferred an entire supply of data characters to apply a control signal to said bus, and said decoding means of said scanning means being conditioned by said control signal to reinitiate said generation of said address codes.