Patent US3967307A successfully refreshed from Google Patents.
US3967307A
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US
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Lateral bipolar transistor for integrated circuits and method for forming the same
Assignee: Signetics Corp
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Filing: 1975-07-10
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Granted: 1976-06-29
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Expires: 1995-07-10
Abstract
Abstract An integrated circuit and method for forming the same including a lateral bipolar transistor having an increased current gain. Floating islands are formed in the emitter of the lateral transistor to have a conductivity type opposite that of the emitter and which act to channel current towards the periphery of the emitter, thereby directing the current towards the collector region. In addition, the integrated circuit includes a buried layer underlying the lateral transistor with the buried layer pinched very thin along a region which outlines the edge of the emitter for enhancing lateral current flow.
Inventors
- 👤 Richard S. Muller
- 👤 Lewis K. Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:39
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/134; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/007; Y10S148/037; Y10S148/096; Y10S148/145; Y10S148/151
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
153 words
In an integrated circuit a lateral bipolar transistor having increased current gain comprising a semiconductor substrate of a first conductivity type having an epitaxial semiconductor layer of a second conductivity type formed thereon, a buried layer of said second conductivity type formed between said epitaxial layer and substrate, an emitter region of said first conductivity type formed in said epitaxial layer overlying the buried layer and extending to the surface of said epitaxial layer with a PN emitter base junction being defined between the emitter region and the epitaxial layer, means for enhancing lateral current from said emitter region to said collector region and for retarding current flow in a vertical sense perpendicular to the lateral direction said enhancing means including at least one island of second conductivity type formed in said emitter region and further including a collector region formed in said epitaxial layer spaced from and adjacent to said emitter region.
Claim 2
Dependent Claim
153 words
In an integrated circuit a lateral bipolar transistor having increased current gain comprising a semiconductor substrate of a first conductivity type having an epitaxial semiconductor layer of a second conductivity type formed thereon, a buried layer of said second conductivity type formed between said epitaxial layer and substrate, an emitter region of said first conductivity type formed in said epitaxial layer overlying the buried layer and extending to the surface of said epitaxial layer with a PN emitter base junction being defined between the emitter region and the epitaxial layer, means for enhancing lateral current from said emitter region to said collector region and for retarding current flow in a vertical sense perpendicular to the lateral direction said enhancing means including at least one island of second conductivity type formed in said emitter region and further including a collector region formed in said epitaxial layer spaced from and adjacent to said emitter region.
Claim 3
Dependent Claim
32 words
An integrated circuit in accordance with claim 1 wherein said collector region comprises a region of said first conductivity type formed in said epitaxial layer surrounding and spaced from said emitter region.
Claim 4
Dependent Claim
31 words
An integrated circuit in accordance with claim 1 wherein said collector region comprises metallization contacting said epitaxial layer to form a Schottky barrier-type collector surrounding and spaced from said emitter region.
Claim 5
Dependent Claim
50 words
An integrated circuit in accordance with claim 1 including a buried layer of said second conductivity type formed between said epitaxial layer and substrate and being necked down to a smaller width generally below the portions of said PN emitter base junction extending to the surface of said epitaxial layer.
References Cited (Backward Citations)
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US3519898A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-29 | 1979-12-29 | 1980-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-29 | 1983-12-29 | 1984-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-29 | 1987-12-29 | 1988-06-29 | $7700.00 | Window Closed / Lapsed |