Comparator device

Claim 2

A comparator device comprising a plurality of coincidence circuits having first input terminals supplied with the corresponding number of bit signals being compared, each having one second input terminal supplied with one of comparison base bit signals, and producing a coincidence detection signal when all the bit signals for each coincidence circuit have the same logical level as that of the comparison base bit signals for that coincidence circuit; and an AND circuit for obtaining the logical product of outputs from the plural coincidence circuits, wherein the number m of the coincidence circuits is so chosen as to satisfy the relationship 2.sup.m.sup.-1 ≦ x ≦ 2.sup.m - 1 with the total number of bit signals being compared designated as x (x ≧ 3).

Claim 3

A comparator device according to claim 1, wherein each coincidence circuit comprises a plurality of exclusive OR circuits each having two input terminals respectively connected to one of the first input terminals and the second input terminal of said coincidence circuit and an AND circuit supplied with output signals from said plural exclusive OR circuits.

Claim 4

A comparator device according to claim 1, wherein each coincidence circuit comprises an AND circuit and NOR circuit each having a plurality of input terminals, one of which is connected to the second input terminal of said coincidence circuit and the others of which are connected to the corresponding ones of the first input terminals of said coincidence circuit; and an OR circuit supplied with output signals from said last mentioned AND and NOR circuits.

Claim 5

An I/O device control unit connected between a CPU and at least one I/O register to control the reading of information from, and the writing thereof in, the I/O register, which comprises an address register stored with address information supplied from the CPU; the comparator device according to claim 1 for carrying out comparison between the bit signals constituting address information stored in the address register and the prescribed comparison base bit signals; a decoder for decoding the bit signals of address information stored in the address register; a gate circuit connected between the decoder and I/O register; and a timing control circuit for delivering a set timing signal to the address register upon receipt of a control signal from the CPU, an operation mode-designating signal to the I/O register and a gate signal to the gate circuit.

Claim 6

An I/O device control unit according to claim 4, wherein the address reigster comprises a plurality of bit units, each bit unit comprising an address information input terminal; a first gate connected to said address information input terminal and controlled by said set timing signal; first and second inverters connected in series between the output terminal of said first gate and the comparator device; a third inverter for reversing the polarity of said set timing signal; and a feedback loop including a second gate connected between the input side of the first inverter and the output side of the second inverter and designed to have its operation controlled by an output signal from the third inverter.

Claim 7

An I/O device control unit according to claim 4, wherein the timing control circuit comprises a first inverter for reversing the polarity of a first control signal from the CPU; a first AND circuit supplied with an output signal from the first inverter and a second control signal from the CPU; a second inverter for reversing the polarity of the second control signal; a second AND circuit supplied with an output signal from the second inverter and the first control signal; a flip-flop circuit reset by an output signal from the first AND circuit and set by an output signal from the second AND circuit, thereby generating an operation mode-designating signal; a third AND circuit supplied with the first and second control signals; a first monostable multivibrator driven by an output signal from said third AND circuit to give forth a set timing signal; an exclusive OR circuit supplied with said first and second control signals; a fourth AND circuit supplied with output signals from said exclusive OR circuit and said comparator device; a delay circuit for delaying the issue of an output signal from said fourth AND circuit a prescribed length of time; and a second monostable multivibrator driven by an output signal from said delay circuit to produce said gate signal.