Patent US3959040A successfully refreshed from Google Patents.
US3959040A
Expired / Lapsed
US
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Compound diffused regions for emitter-coupled logic circuits
Assignee: Motorola Solutions Inc
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Filing: 1971-09-01
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Granted: 1976-05-25
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Expires: 1991-09-01
Abstract
Abstract There is provided a method and apparatus for use in fabrication of emitter-coupled logic circuits in integrated circuit form in which the base regions for transistor-transistor logic transistors and tub regions for emitter resistors for use in these circuits are fabricated utilizing a compound diffusion process. The use of the compound diffusion process both reduces spiking problems prevalent with emitter resistors while at the same time enabling the appropriate doping concentrations in the bases of both the ECL transistors and the TTL transistors to be established by opening up these regions during specified portions of the fabrication process.
Inventors
- 👤 Phillip W. Robertson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10D84/201; H10D84/204; H10D84/209; H10D84/641; H10D84/642; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
167 words
In a method for forming a logic circuit in monolithic integrated circuit form, said logic circuit having an emitter-coupled logic transistor and an emitter resistor, the improvement comprising the steps of: providing a semiconductor region of a first conductivity-type having a layer of a second conductivity-type contiguous therewith, said layer having a surface; masking the surface of the layer with a first mask; opening up said first mask at locations at which the base region for the emitter-coupled logic transistor and the tub region for said emitter resistor are to be formed; diffusing into said layer at said locations a dopant to a concentration suitable for forming said base region and said tub region; remasking said surface of said layer with a second mask; opening up said second mask over said emitter resistor tub region; and diffusing into said tub region a dopant to a concentration which brings the doping concentration in said tub region to a level sufficient to eliminate spiking in a finished emitter resistor.
Claim 2
Dependent Claim
167 words
In a method for forming a logic circuit in monolithic integrated circuit form, said logic circuit having an emitter-coupled logic transistor and an emitter resistor, the improvement comprising the steps of: providing a semiconductor region of a first conductivity-type having a layer of a second conductivity-type contiguous therewith, said layer having a surface; masking the surface of the layer with a first mask; opening up said first mask at locations at which the base region for the emitter-coupled logic transistor and the tub region for said emitter resistor are to be formed; diffusing into said layer at said locations a dopant to a concentration suitable for forming said base region and said tub region; remasking said surface of said layer with a second mask; opening up said second mask over said emitter resistor tub region; and diffusing into said tub region a dopant to a concentration which brings the doping concentration in said tub region to a level sufficient to eliminate spiking in a finished emitter resistor.
Claim 3
Dependent Claim
77 words
The method of claim 1 further including the steps of: again remasking said surface of said layer with a third mask; opening up said third mask over locations at which emitters for said transistor and for said resistor are to be located; and diffusing a dopant through said openings for forming said emitters, whereby all emitter regions are formed simultaneously with the relative diffusion depths automatically controlled by the doping concentration in said base and tub regions.
Claim 4
Dependent Claim
110 words
The method of claim 1 wherein said logic circuit further includes a transistor-transistor logic transistor, said first mask is also opened up at a location for the base region for said transistor-transistor logic transistor, said base region is formed by diffusion while diffusing to form the base region for said emitter-coupled logic transistor and the tub region for said emitter resistor, said second mask is also opened up over the transistor-transistor logic transistor base region, and diffusion into said base region is carried out to a concentration which brings the doping concentration in said base region to a level commensurate with the low betas necessary for said transistor-transistor logic transistor.
Claim 5
Dependent Claim
77 words
The method of claim 3 further including the steps of: again remasking said surface of said layer with a third mask; opening up said third mask over locations at which emitters for said transistors and for said resistor are to be located; and diffusing a dopant through said openings for forming said emitters, whereby all emitter regions are formed simultaneously with the relative diffusion depths automatically controlled by the doping concentrations in said base and tub regions.
Claim 6
Dependent Claim
55 words
The method of claim 4 wherein said logic circuit further includes a diffused resistor, said second mask is also opened up over the location at which said diffused resistor is to be formed, and diffusion into said location is carried out to a concentration sufficient to provide a high resistance value for said diffused resistor.
Claim 7
Dependent Claim
37 words
The method as recited in claim 5 wherein the final sheet resistivity of the base regions of said emitter-coupled logic transistor measured at the surfaces of said base regions is between 290 and 310 ohms per square.
Claim 8
Dependent Claim
89 words
The method as recited in claim 5 wherein the diffusion steps comprise: forming on said layer a solution of doping material; removing excess solvent from said solution; heating said doping material in an inert atmosphere such that a predictable dopant distribution occurs at the surface of said layer, whereby a sheet resistivity lower than that required occurs; removing the excess doping material from said epitaxial layer; and subjecting said layer to hot steam treatments and oxygen drying steps so as to raise the sheet resistivity of the diffused region.
Claim 9
Dependent Claim
31 words
The method as recited in claim 7 wherein the steam treatments are carried out to obtain a surface sheet resistivity for the double diffused regions of approximately 60 ohms per square.
Claim 10
Dependent Claim
45 words
The method as recited in claim 8 wherein the steam treatments are carried out to obtain a sheet resistivity for said diffused resistors of between 95 and 102 ohms per square and for said emitter-coupled logic transistors of between 290 and 310 ohms per square.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-25 | 1979-11-24 | 1980-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-25 | 1983-11-24 | 1984-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-25 | 1987-11-24 | 1988-05-25 | $7700.00 | Window Closed / Lapsed |