Semiconductor device

Claim 2

In a semiconductor device of a high blocking voltage comprising: a semiconductor substrate having a pair of mutually opposing principal surfaces disposed substantially in parallel with each other and a side surface connecting the principal surfaces and including between said pair of principal surfaces at least a first layer of one conductivity type, a second layer of the other conductivity type having in a uniform distribution a lower impurity concentration than that of said first layer, disposed adjacent to and forming a first PN junction with said first layer, and a third layer of said one conductivity type having a higher impurity concentration than that of said second layer, disposed adjacent to and forming a second PN junction with said second layer, said first and second PN junctions being exposed at said side surface, said side surface being formed into a pulley-shape the valley portion of which is located substantially at the middle of said second layer; a cover member of a high dielectric constant filling up the valley portion of the pulley shape; and a pair of main electrodes provided respectively in ohmic contact with said principal surfaces, in which the greater part of a depletion layer produced when the first or second PN junction is reversely biased exists in said second layer and spreads beyond said valley portion; the improvement comprising the fact that said pulley shape of the side surface satisfies the condition ##EQU6## where d represents the depth of the valley portion, w the thickness of the semiconductor substrate, and ε the specific dielectric constant of the atmosphere around the valley portion, and wherein the ratio d/w of the valley depth to the substrate thickness is not larger than unity.

Claim 3

A semiconductor device according to claim 1, further comprising a cover layer of a dielectric constant lower than that of said cover member covering the side surface of the pulley-shape.

Claim 4

A semiconductor device according to claim 1, wherein said semiconductor substrate further comprises a fourth layer of said other conductivity type, having a higher impurity concentration than that of said third layer, embedded in and forming a third PN junction with said third layer, and having a surface aligned with a corresponding one of said principal surfaces so as to be exposed, one of said main electrodes being disposed on said exposed surface of said fourth layer.

Claim 5

A semiconductor device according to claim 3, further comprising a cover layer of a dielectric constant lower than that of said cover member covering the side surface of the pulley-shape.

Claim 6

A semiconductor device according to claim 3, further comprising a control electrode disposed on the principal surface from which said fourth layer is exposed, apart from the main electrode provided on the surface of said fourth layer.

Claim 7

A semiconductor device according to claim 3, wherein inflection points are formed in the pulley-shape near the exposed first and second PN junctions.

Claim 8

A semiconductor device according to claim 6, further comprising a cover layer of a dielectric constant lower than that of said cover member covering the side surface of the pulley-shape.

Claim 9

A semiconductor device according to claim 6, further comprising a control electrode disposed on the principal surface from which said fourth layer is exposed, apart from the main electrode provided on the surface of said fourth layer.

Claim 10

In a semiconductor device of a high blocking voltage comprising: a semiconductor substrate having a pair of mutually opposing principal surfaces disposed substantially in parallel with each other and a side surface connecting the principal surfaces and including between said pair of principal surfaces a first layer of one conductivity type, a second layer of the other conductivity type having in a uniform distribution a lower impurity concentration than that of said first layer, disposed adjacent to and forming a first PN junction with said first layer, a third layer of said one conductivity type having a higher impurity concentration than that of said second layer, disposed adjacent to and forming a second PN junction with said second layer, and a fourth layer of said other conductivity type, having a higher impurity concentration than that of said third layer, embedded in and forming a third PN junction with said third layer, and having a surface aligned with a corresponding one of said principal surfaces so as to be exposed, said first and second PN junctions being exposed at said side surface, said side surface being formed into a pulley-shape the valley portion of which is located substantially at the middle of said second layer; a cover member of a high dielectric constant filling up the valley portion of the pulley-shape; and a pair of main electrodes provided in ohmic contact with said first and fourth layers on said principal surfaces, respectively, in which the greater part of a depletion layer produced when the first or second PN junction is reversely biased exists in said second layer and spreads beyond said valley portion; the improvement comprising the fact that the ratio d/w of the depth d of the valley portion to the thickness w of the semiconductor substrate is larger than the value corresponding to the line connecting points A, B, C and D of FIG. 3, and wherein the ratio d/w of the valley depth to the substrate thickness is not larger than unity.

Claim 11

In a semiconductor device of a high blocking voltage comprising: a semiconductor substrate having a pair of mutually opposing principal surfaces disposed substantially in parallel with each other and a side surface connecting the principal surfaces and including between said pair of principal surfaces a first layer of one conductivity type, a second layer of the other conductivity type having in a uniform distribution a lower impurity concentration than that of said first layer, disposed adjacent to and forming a first PN junction with said first layer, a third layer of said one conductivity type having a higher impurity concentration than that of said second layer, disposed adjacent to and forming a second PN junction with said second layer, and a fourth layer of said other conductivity type, having a higher impurity concentration than that of said third layer, embedded in and forming a third PN junction with said third layer, and having a surface aligned with a corresponding one of said principal surfaces so as to be exposed, said first and second PN junctions being exposed at said side surface, said side surface being formed into a pulley-shape the valley portion of which is located substantially at the middle of said second layer; a cover member of a high dielectric constant filling up the valley portion of the pulley-shape; and a pair of main electrodes provided in ohmic contact with said first and fourth layers on said principal surfaces, respectively, in which the greater part of a depletion layer produced when the first or second PN junction is reversely biased exists in said second layer and spreads beyond said valley portion; the improvement comprising the fact that the ratio d/w of the depth d of the valley portion to the thickness w of the semiconductor substrate is larger than the value corresponding to the line connecting points A, B, C and D of FIG. 3, and wherein the ratio d/w of the valley depth to the substrate thickness is not larger than unity.

Claim 12

A semiconductor device according to claim 9, further comprising a cover layer of a dielectric constant lower than that of said cover member covering the side surface of the pulley-shape.

Claim 13

A semiconductor device according to claim 9, further comprising a control electrode disposed on the principal surface from which said fourth layer is exposed, apart from the main electrode provided on the surface of said fourth layer.

Claim 14

A semiconductor device according to claim 10, further comprising a control electrode disposed on the principal surface from which said fourth layer is exposed, apart from the main electrode provided on the surface of said fourth layer.