← Back to Patent Explorer
US3648340A Expired / Lapsed US ⏱️ 0.0 years remaining

Hybrid solid-state voltage-variable tuning capacitor

Assignee: Motors Liquidation Co
•
Filing: 1969-08-11
•
Granted: 1972-03-14
•
Expires: 1989-08-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A hybrid varactor including a surface varactor and a junction varactor. One form of the hybrid varactor includes the PNjunction of the junction varactor contiguous the semiconductorinsulator interface of the surface varactor. The capacitance of the device is primarily due to the space-charge depletion region associated with the semiconductor-insulator interface. The PNjunction functions primarily to prevent inversion at the semiconductor-insulator interface.

Inventors

  • 👤 Bernard A Maciver

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 08:34
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 104 words
A method of making a hybrid varactor which comprises: epitaxially depositing a high-resistivity layer of semiconductive material on a low-resistivity semiconductive wafer of the same conductivity type; coating the surface of said epitaxial layer with an insulating material; etching through said coating to expose a preselected area of said epitaxial layer; forming on said insulating coating and said preselected area a counterelectrode containing P-type impurity metal; alloying said counterelectrode to form a PN-junction with said preselected area and with any other epitaxial areas exposed through pinholes in said insulating coating; and attaching an electrode to said wafer on a surface spaced from said layer.
Claim 2
Independent Claim 104 words
A method of making a hybrid varactor which comprises: epitaxially depositing a high-resistivity layer of semiconductive material on a low-resistivity semiconductive wafer of the same conductivity type; coating the surface of said epitaxial layer with an insulating material; etching through said coating to expose a preselected area of said epitaxial layer; forming on said insulating coating and said preselected area a counterelectrode containing P-type impurity metal; alloying said counterelectrode to form a PN-junction with said preselected area and with any other epitaxial areas exposed through pinholes in said insulating coating; and attaching an electrode to said wafer on a surface spaced from said layer.
Claim 3
Independent Claim 110 words
A method of making a hybrid varactor which comprises: epitaxially depositing a high-resistivity layer of semiconductive material on a low-resistivity semiconductive wafer of the same conductivity type; coating the surface of said epitaxial layer with a thin layer of silicon oxide; coating the silicon oxide layer with a thicker layer of an oxide selected from the group consisting of Nb2O5, Ta2O5 and TiO2; etching through said oxide layers to expose a preselected area of said epitaxial layer; forming a PN-junction within said preselected area; applying a counterelectrode to said preselected area and the surrounding oxide layers; and attaching an electrode to said wafer on a surface spaced from said layers.
Claim 4
Independent Claim 110 words
A method of making a hybrid varactor which comprises: epitaxially depositing a high-resistivity layer of semiconductive material on a low-resistivity semiconductive wafer of the same conductivity type; coating the surface of said epitaxial layer with a thin layer of silicon oxide; coating the silicon oxide layer with a thicker layer of an oxide selected from the group consisting of Nb2O5, Ta2O5 and TiO2; etching through said oxide layers to expose a preselected area of said epitaxial layer; forming a PN-junction within said preselected area; applying a counterelectrode to said preselected area and the surrounding oxide layers; and attaching an electrode to said wafer on a surface spaced from said layers.

References Cited (Backward Citations)

US3382568A Cited
US3508123A Cited
US3568014A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-03-14 1975-09-13 1976-03-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-03-14 1979-09-13 1980-03-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-03-14 1983-09-13 1984-03-14 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag