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Patent US3943347A successfully refreshed from Google Patents.
US3943347A
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Data processor reorder random access memory
Assignee: RCA Corp
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Filing: 1974-11-27
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Granted: 1976-03-09
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Expires: 1994-11-27
Abstract
Abstract Random access memory addressing system for mapping data into a memory according to one schema and retrieving the stored data according to another schema using minimum storage locations.
Inventors
- 👤 Lloyd William Martinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
160 words
In a system for coupling output signals from a first processor to the input means of a second processor wherein the input signals to said second processor are represented by a different schema from the schema of the output signals from said first processor, the improvement comprisng: first memory means for storing the output signals from said first processor, said first memory means having data input means, data output means, and addressing means; second memory means for storing signals specifying a first group of first memory addresses corresponding to the schema of input signals to said second processor, said second memory having addressing means and output means; timing signal means for producing a pluraity of signals in time sequence representing successive binary numbers; means for coupling said timing signals to the addressing means of said first memory means as a first address; means for coupling a subset of said timing signals to the addressing means of said second memory means;
Claim 2
Dependent Claim
160 words
In a system for coupling output signals from a first processor to the input means of a second processor wherein the input signals to said second processor are represented by a different schema from the schema of the output signals from said first processor, the improvement comprisng: first memory means for storing the output signals from said first processor, said first memory means having data input means, data output means, and addressing means; second memory means for storing signals specifying a first group of first memory addresses corresponding to the schema of input signals to said second processor, said second memory having addressing means and output means; timing signal means for producing a pluraity of signals in time sequence representing successive binary numbers; means for coupling said timing signals to the addressing means of said first memory means as a first address; means for coupling a subset of said timing signals to the addressing means of said second memory means;
Claim 3
Dependent Claim
122 words
first adder means responsive to said output means of said second memory and to said timing signals for producing sum output signals; means for coupling said sum output signals from said first adder means to the addressing means of said first memory means as a second address; means responsive to said timing signals for storing data in said first memory means at one of said addresses and for retrieving data from said first memory means at the other of said addresses; means for coupling the output signals from said first processor to the data input means of said first memory means; and means for coupling the data output means from said first memory means to the input means of said second processor.
Claim 4
Dependent Claim
122 words
first adder means responsive to said output means of said second memory and to said timing signals for producing sum output signals; means for coupling said sum output signals from said first adder means to the addressing means of said first memory means as a second address; means responsive to said timing signals for storing data in said first memory means at one of said addresses and for retrieving data from said first memory means at the other of said addresses; means for coupling the output signals from said first processor to the data input means of said first memory means; and means for coupling the data output means from said first memory means to the input means of said second processor.
Claim 5
Dependent Claim
60 words
The invention claimed in claim 1 wherein said first memory means comprises a pluraity of submemory means, each having input means, output means, and addressing means; means for producing signals representative of constants; and further adder means responsive to said constants signals and the sum signals from said first adder means for producing second address signals to said submemory systems.
Claim 6
Dependent Claim
32 words
The invention as claimed in claim 2 further including control means for altering the address to said second memory whereby said data is coupled to said secondary processor according to another schema.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-09 | 1979-09-08 | 1980-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-09 | 1983-09-08 | 1984-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-09 | 1987-09-08 | 1988-03-09 | $7700.00 | Window Closed / Lapsed |