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US3930232A Expired / Lapsed US ⏱️ 0.0 years remaining

Format insensitive digital computer

Assignee: Raytheon Co
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Filing: 1973-11-23
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Granted: 1975-12-30
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Expires: 1993-11-23
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Abstract

Abstract A digital computer wherein data words representing different data types, such as fixed point numbers, floating point numbers of logical statements, are retrieved from memory in any order required during execution of a program and, after conversion to a predetermined format, are applied to an arithmetic unit for processing. To accomplish the conversion, logic circuitry is provided to identify, during execution of a program, the data type of each retrieved data word and to change the format of each such word to the predetermined format for processing in the arithmetic unit. Additional logic circuitry is provided to respond to each data word out of the arithmetic unit to reconvert each such word back into a format for storage in memory.

Inventors

  • 👤 Steven J Wallach
  • 👤 Alan J Deerfield
  • 👤 Stanley M Nissen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 23:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30025; G06F5/00; G06F5/01; G06F5/012

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 377 words
In a digital computer including a memory wherein single precision words may be stored at respective single memory locations and double precision words may be stored at two contiguous memory locations as two single precision words, each one of such words, other than instruction words, including an ''''m'''' bit operand code field, where ''''m'''' is the number of bits making up an operand code in any one of a plurality of formats including logical statements, fixed point numbers, floating point single precision numbers and floating point double precision numbers and an ''''n'''' bit data type code indicative of the format of the operand, and a processor wherein each operand retrieved from the memory during execution of a program may be processed, the improvement comprising a. a plurality, corresponding in number to the number of different formats of operands, of first format conversion means for changing the format of each single precision word retrieved from the memory during execution of a program, each different one of such first format conversion means being actuated by a different one of the data type codes in each single precision word to convert each operand retrieved from the memory to a particular format of a floating point, double precision word of 2(m + n) bits and to combine the two single precision words making up each double precision word retrieved from the memory into said particular format, the states of selected bits in each said particular format floating point double precision word being indicative of the data type code corresponding to each operand retrieved from the memory; b. means, responsive to each said particular format floating point, double precision word for processing each such word, the states of the selected bits remaining unchanged during processing; and c. a plurality, corresponding in number to the number of different formats of operands, of second format conversion means, each different one of such second format conversion means being responsive to the states of the selected bits in each one of said particular format floating point, double precision words out of the processing means to convert each such one to a format corresponding to the original format of the single or double precision words stored in the memory in single or two contiguous memory locations, respectively.
Claim 2
Dependent Claim 377 words
In a digital computer including a memory wherein single precision words may be stored at respective single memory locations and double precision words may be stored at two contiguous memory locations as two single precision words, each one of such words, other than instruction words, including an ''''m'''' bit operand code field, where ''''m'''' is the number of bits making up an operand code in any one of a plurality of formats including logical statements, fixed point numbers, floating point single precision numbers and floating point double precision numbers and an ''''n'''' bit data type code indicative of the format of the operand, and a processor wherein each operand retrieved from the memory during execution of a program may be processed, the improvement comprising a. a plurality, corresponding in number to the number of different formats of operands, of first format conversion means for changing the format of each single precision word retrieved from the memory during execution of a program, each different one of such first format conversion means being actuated by a different one of the data type codes in each single precision word to convert each operand retrieved from the memory to a particular format of a floating point, double precision word of 2(m + n) bits and to combine the two single precision words making up each double precision word retrieved from the memory into said particular format, the states of selected bits in each said particular format floating point double precision word being indicative of the data type code corresponding to each operand retrieved from the memory; b. means, responsive to each said particular format floating point, double precision word for processing each such word, the states of the selected bits remaining unchanged during processing; and c. a plurality, corresponding in number to the number of different formats of operands, of second format conversion means, each different one of such second format conversion means being responsive to the states of the selected bits in each one of said particular format floating point, double precision words out of the processing means to convert each such one to a format corresponding to the original format of the single or double precision words stored in the memory in single or two contiguous memory locations, respectively.

References Cited (Backward Citations)

US3037701A Cited
US3460095A Cited
US3389379A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-12-29 1979-06-30 1979-12-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-12-29 1983-06-30 1983-12-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-12-29 1987-06-30 1987-12-30 $7700.00 Window Closed / Lapsed

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