Data converter for a computer system

Claim 3

A data converting apparatus for converting a first data of a first predetermIned number of binary digits into a second data of a second predetermined number of binary digits and vice versa in response to first and second data-conversion signals supplied from a central data processor, respectively, said first data including letter data and numerical data, said apparatus comprising a first decision circuit for discriminating whether a portion of said first data is letter data or numerical data; a second decision circuit for discriminating whether a portion of said second data is one that is converted from said letter data or from said numerical data; an output timing signal generating circuit for generating first and second control signals upon receipt of the first and the second data-conversion signals, respectively, said first and second control signals being used for conversion of the first data into the second data and of the second data into the letter data or the numerical data in response to the outputs of said first and second decision circuits, respectively; a first data converting circuit responsive to said first control signal for adding a first additional code to said letter data for converting said first data into said second data, for packing a predetermined number of serial bits of said numerical data into the second data after omitting redundant bits not relative to the expression of the contents thereof and for adding a second additional code thereto; and a second data converting Circuit responsive to said second control signal for converting portions of the second data having said first additional code into said letter data, for converting portions of the second data having said second additional code into numerical data, and for converting portions of the second data having neither the first nor second additional codes into a predetermined plural number of numerical data.

Claim 4

A data converting apparatus for converting a first data of a first predetermIned number of binary digits into a second data of a second predetermined number of binary digits and vice versa in response to first and second data-conversion signals supplied from a central data processor, respectively, said first data including letter data and numerical data, said apparatus comprising a first decision circuit for discriminating whether a portion of said first data is letter data or numerical data; a second decision circuit for discriminating whether a portion of said second data is one that is converted from said letter data or from said numerical data; an output timing signal generating circuit for generating first and second control signals upon receipt of the first and the second data-conversion signals, respectively, said first and second control signals being used for conversion of the first data into the second data and of the second data into the letter data or the numerical data in response to the outputs of said first and second decision circuits, respectively; a first data converting circuit responsive to said first control signal for adding a first additional code to said letter data for converting said first data into said second data, for packing a predetermined number of serial bits of said numerical data into the second data after omitting redundant bits not relative to the expression of the contents thereof and for adding a second additional code thereto; and a second data converting Circuit responsive to said second control signal for converting portions of the second data having said first additional code into said letter data, for converting portions of the second data having said second additional code into numerical data, and for converting portions of the second data having neither the first nor second additional codes into a predetermined plural number of numerical data.

Claim 5

The apparatus of claim 2, further comprising first storing means having said first predetermined number of stages and coupled to said first decision circuit and said timing signal generating circuit, second storing means having said second predetermined number of stages and coupled to said second decision circuit and said timing signal generating circuit, and data converting means including said first and second data converting circuits coupled between said first and second storing means and said timing signal generating circuit.

Claim 6

The apparatus of claim 3, in which said first data converting circuit comprises said second predetermined number of amplifiers, each of said amplifiers having an output coupled respectively to the stages of said second storing means and an input, and logic means respectively coupled intermediate inputs of said amplifiers and the stages of said first storage means and said first decision circuit.

Claim 7

The apparatus of claim 3, in which said second data converting circuit comprises said first predetermined number of amplifiers, each of said amplifiers having an output coupled respectively to the stages oF said first storing means and an input, and second loGic means respectively coupled intermediate inputs of said amplifiers and the stages of said second storing means and said second decision circuit.