Patent US3928091A successfully refreshed from Google Patents.
US3928091A
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Method for manufacturing a semiconductor device utilizing selective oxidation
Assignee: Hitachi Ltd
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Filing: 1974-08-12
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Granted: 1975-12-23
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Expires: 1994-08-12
Abstract
Abstract An N region and a P region adjacent thereto are formed on a major surface of a P silicon substrate, an N silicon layer is epitaxially grown on the major surface and the epitaxial layer is partially oxidized using silicon nitride as a mask therefor, so as to form an SiO2 layer reaching the P and N regions with a ring shape, whereby the N silicon layer surrounded by the SiO2 layer is electrically isolated from the other portions of the N silicon layer substantially without leakage current.
Inventors
- 👤 Seiichi Tachi
- 👤 Hideki Moriyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:07
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10P; H10P14/00; H10P14/60; H10P14/61; H10W10/10; H10W10/13; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/007; Y10S148/036; Y10S148/037; Y10S148/085; Y10S148/117
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: A. FORMING A FIRST SEMICONDUCTOR REGION OF A FIRST CONDUCTIVITY TYPE AND A RELATIVELY LOW RESISTIVITY PARTIALLY ON A MAJOR SURFACE OF A SEMICONDUCTOR SUBSTRATE OF A SECOND CONDUCTIVITY TYPE AND A RELATIVELY HIGH RESISTIVITY; B. FORMING A SECOND SEMICONDUCTOR REGION OF THE SECOND CONDUCTIVITY TYPE AND A RELATIVELY LOW RESISTIVITY ON THE MAJOR SURFACE OF THE SUBSTRATE EXCEPT FOR THE SURFACE OF SAID FIRST SEMICONDUCTOR REGION; C. DEPOSITING A SEMICONDUCTOR LAYER OF THE FIRST CONDUCTIVITY TYPE AND A RELATIVELY HIGH RESISTIVITY, SO AS TO EMBED SAID FIRST AND SECOND SEMICONDUCTOR REGIONS THEREUNDER; AND D. SELECTIVELY OXIDIZING SAID SEMICONDUCTOR LAYER FROM THE SURFACE THEREOF, SO AS TO FORM AN INSULATING LAYER OF THE SEMICONDUCTOR MATERIAL EXTENDING TO SAID SECOND SEMICONDUCTOR REGION IN SAID SEMICONDUCTOR LAYER, SAID INSULATING LAYER BEING CONNECTED TO SAID SECOND SEMICONDUCTOR REGION AT THE BOTTOM SURFACE THEREOF AND SURROUNDING THE PORTION OF SAID SEMICONDUCTOR LAYER FORMED ON SAID FIRST SEMICONDUCTOR REGION AT THE SIDE SURFACE THEREOF.
Claim 2
Independent Claim
170 words
A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF: A. FORMING A FIRST SEMICONDUCTOR REGION OF A FIRST CONDUCTIVITY TYPE AND A RELATIVELY LOW RESISTIVITY PARTIALLY ON A MAJOR SURFACE OF A SEMICONDUCTOR SUBSTRATE OF A SECOND CONDUCTIVITY TYPE AND A RELATIVELY HIGH RESISTIVITY; B. FORMING A SECOND SEMICONDUCTOR REGION OF THE SECOND CONDUCTIVITY TYPE AND A RELATIVELY LOW RESISTIVITY ON THE MAJOR SURFACE OF THE SUBSTRATE EXCEPT FOR THE SURFACE OF SAID FIRST SEMICONDUCTOR REGION; C. DEPOSITING A SEMICONDUCTOR LAYER OF THE FIRST CONDUCTIVITY TYPE AND A RELATIVELY HIGH RESISTIVITY, SO AS TO EMBED SAID FIRST AND SECOND SEMICONDUCTOR REGIONS THEREUNDER; AND D. SELECTIVELY OXIDIZING SAID SEMICONDUCTOR LAYER FROM THE SURFACE THEREOF, SO AS TO FORM AN INSULATING LAYER OF THE SEMICONDUCTOR MATERIAL EXTENDING TO SAID SECOND SEMICONDUCTOR REGION IN SAID SEMICONDUCTOR LAYER, SAID INSULATING LAYER BEING CONNECTED TO SAID SECOND SEMICONDUCTOR REGION AT THE BOTTOM SURFACE THEREOF AND SURROUNDING THE PORTION OF SAID SEMICONDUCTOR LAYER FORMED ON SAID FIRST SEMICONDUCTOR REGION AT THE SIDE SURFACE THEREOF.
Claim 3
Dependent Claim
55 words
A method for manufacturing a semiconductor device according to claim 1, further including the step of forming a ring-shaped groove in said semiconductor layer, the bottom of said groove extending over at least a portion of said second semiconductor region, and surrounding said first semiconductor region, subsequent to step (c) and prior to step (d).
Claim 4
Dependent Claim
52 words
A method for manufacturing a semiconductor device according to claim 1, wherein said step (c) comprises the step of epitaxially depositing said semiconductor layer upon said first and second semiconductor regions, so that the conductivity determining impurity of said second semiconductor region moves into said epitaxially deposited layer during the deposition thereof.
Claim 5
Dependent Claim
52 words
A method for manufacturing a semiconductor device according to claim 2, wherein said step (c) comprises the step of epitaxially depositing said semiconductor layer upon said first and second semiconductor regions, so that the conductivity determining impurity of said second semiconductor region moves into said epitaxially deposited layer during the deposition thereof.
Claim 6
Dependent Claim
36 words
A method for manufacturing a semiconductor device according to claim 1, further including the step of forming at least one additional semiconductor region in said deposited semiconductor layer to form at least one pn junction therein.
Claim 7
Dependent Claim
37 words
A method for manufacturing a semiconductor device according to claim 2, wherein said steps (a) and (b) each comprises diffusing respective first and second conductivity type determining impurities into said substrate to first and second respective depths.
Claim 8
Dependent Claim
36 words
A method for manufacturing a semiconductor device according to claim 2, wherein step (b) comprises the step of growing a heavily doped second conductivity type layer on the surface of said substrate adjacent said first region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-22 | 1979-06-23 | 1979-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-22 | 1983-06-23 | 1983-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-22 | 1987-06-23 | 1987-12-23 | $7700.00 | Window Closed / Lapsed |