Self aligned CCD element fabrication method therefor

Claim 1

A process for fabricating a self-aligned charge-coupled semiconductor structure comprising the steps of: a. forming at least one insulating layer on one surface of a semiconductor substrate; b. forming a layer of electrically conducting material on said at least one insulating layer; c. forming an overlying insulating layer on said layer of electrically conducting material; d. removing portions of said overlying insulating layer at regular intervals to demarcate the location of barrier regions to be formed in underlying registration in said substrate; e. forming implanted barrier regions in the top-most portion of said semiconductor substrate at regular intervals along said substrate; f. forming filled-in insulating regions within said removed portions, wherein said filled-in insulating regions are of a material different from said overlying insulating layer; g. removing alternating remaining portions of said overlying insulating layer and those said filled-in insulating regions above a first series of alternate barrier regions to expose portions of said conducting material; h. removing the exposed portions of said conducting material using those still remaining portions of said overlying insulating layer and said filled-in insulating regions as a mask wherein the remaining portions of said layer of conducting material constitute a first set of gate electrodes which have edges in substantial alignment with leading edges of the other alternate series of implanted barrier regions; i. forming insulating material over said first set of gate electrodes; and j. applying a further layer of electrically conducting material over the exposed areas of said at least onE layer of insulating material, said further layer of conducting material forming a second set of gate electrodes having edges in alignment with the leading edges of a second alternate series of said implanted barrier regions.